Define electronic interfaces which the output of the FPGA backend implements
@andrea :
we need to figure out the electronic interface the FPGA should support. is the input being parsed ... a serial input? written into a memory buffer the FPGA has access to? a configurable knob to pick one of these? what does the output look like? if it's just "this parses", a simple true/false signal that varies as the input is processed might do, but do we want to support analogues of h_action() to connect up to other parts of the FPGA in more complex ways?
@kia :
there's not too much freedom in terms of what the IP block for a parsing engine looks like on FPGA fabric, there's the question of "how does it take an input" -- which can either be like, a parallel bus with a configurable width and some sideband signals to indicate packet/document boundaries to initialise or reset parser state; or it can be like a dual ported block RAM (or external DRAM) where the parser IP reads into at some address when it's told to by a sideband signal by whoever is calling it / whoever filled up the RAM with data -- and there's the output format -- which can be either outputting different data elements on different output ports (like if we're parsing an IP header, instantiate a source IP address output port, etc) all at once, or have the parser IP block simulate a chunk of memory where different elements of the parse tree are exposed at different addresses -- and either way there's the need for a sideband signal to indicate successful parse completion
so it'd be not difficult to have a little FPGA-specific stanza that specifies exactly how the generated IP block interfaces with input/output; and also generate the interface boilerplate/state-machinery accordingly