diff --git a/automatic_tester.py b/automatic_tester.py
index b1d431064896b095af9c7da638cf93c023d92eab..95456b93d8d8f4ed9a4e944c63e2b38fcce4474d 100755
--- a/automatic_tester.py
+++ b/automatic_tester.py
@@ -35,7 +35,7 @@ def walk_the_tree(tree, level = 0):
         walk_the_tree(subnode, level + 1)
 
 
-class Cirno(Elaboratable):
+class DUT(Elaboratable):
     def __init__(self):
         self.input_memory_addr = Signal(8)
         self.input_memory_data = Signal(16)
@@ -269,7 +269,7 @@ class Cirno(Elaboratable):
 
 def run_the_sim(parse_me):
     m = Module()
-    m.submodules.baka = nine = Cirno()
+    m.submodules.dut = dut = DUT()
     trace = []
     numwritten = []
     parse_success = [0]
@@ -277,37 +277,37 @@ def run_the_sim(parse_me):
 
     def process():
         while True:
-            z = yield nine.finalized
+            z = yield dut.finalized
 #            print(z)
             if(z==0):
                 yield
-                z = yield nine.finalized
+                z = yield dut.finalized
 #                print(z)
 
                 array = []
                 for idx in range(128):
                     #print(idx)
-                    x = yield nine.tapir[idx]
+                    x = yield dut.tapir[idx]
                     array.append(x)
                 trace.append(array)
             else:
                 yield
                 yield
-                xz = yield nine.numwritten
-                parse_success[0] = yield nine.parse_success
+                xz = yield dut.numwritten
+                parse_success[0] = yield dut.parse_success
                 numwritten.append(xz)
                 print("NUM WRITTEN INSIDE", numwritten)
                 print("PARSE SUCCESS,", parse_success)
                 break
 
 
-    with m.Switch(nine.input_memory_addr):
+    with m.Switch(dut.input_memory_addr):
         for addr,data in enumerate(parse_me):
             with m.Case(addr):
                 #print(addr,data)
-                m.d.sync += nine.input_memory_data.eq(data)
+                m.d.sync += dut.input_memory_data.eq(data)
         with m.Default():
-                m.d.sync += nine.input_memory_data.eq(0xf00d)
+                m.d.sync += dut.input_memory_data.eq(0xf00d)
 
 
     sim = Simulator(m)