diff --git a/rtl_lib/arbitrary_width_memory.py b/rtl_lib/arbitrary_width_memory.py
index dad98605034bff4d7b77b40e6d3b73502ddf33fc..4e46f0c420e405d759008438861e6e3eee188e89 100644
--- a/rtl_lib/arbitrary_width_memory.py
+++ b/rtl_lib/arbitrary_width_memory.py
@@ -101,22 +101,17 @@ class ArbitraryWidthMemory(Elaboratable):
             shreg = Signal(self.fake_data_width)
             current_slice = Signal(self.backing_memory_data_width)
             lower_bits_cut = Signal(self.backing_memory_data_width)
+            top_cut = Signal(range(self.backing_memory_data_width+1))
 
             valid_shreg_bits = Signal(range(self.fake_data_width))
             shreg_new_bits = Signal(range(self.backing_memory_data_width+1))
 
-            m.d.sync += shreg.eq(shreg << (shreg_new_bits) | current_slice)
-
             m.d.comb += lower_bits_cut.eq(read_port.data>>LS_bit_index)
-
-            top_cut = Signal(range(self.backing_memory_data_width+1))
-
-            m.d.comb += top_cut.eq(self.backing_memory_data_width-MS_bit_index-1)
+            m.d.comb += top_cut.eq(self.backing_memory_data_width-MS_bit_index-1) #is this correct given there's the lower bit cutting that happens before this? we need to draw it out to be sure
             m.d.comb += current_slice.eq(((lower_bits_cut<<top_cut)&0xff)>>top_cut)
 
             m.d.comb += shreg_new_bits.eq(MS_bit_index-LS_bit_index+1)
 
-
             with m.FSM() as fsm:
                 with m.State("RESET"):
                     m.next ="READY"
@@ -153,6 +148,8 @@ class ArbitraryWidthMemory(Elaboratable):
                         # So here we determine if there's any need for additional memory words:
                         m.d.comb += additional_words.eq(end_bit_pseudo_index[self.backing_memory_data_width_bits:])
 
+                        m.d.sync += shreg.eq(current_slice)
+
                         with m.If(additional_words == 0):
                             # No additional words, calculate which bits we need from the sole word we're fetching:
                             m.d.comb += MS_bit_index.eq(end_bit_pseudo_index[:self.backing_memory_data_width_bits])
@@ -171,6 +168,7 @@ class ArbitraryWidthMemory(Elaboratable):
 
                 with m.State("ADD"):
                     m.d.comb += bus.ready_out.eq(0)
+                    m.d.sync += shreg.eq(shreg << (shreg_new_bits) | current_slice)
 
                     # we handle both the full-word fetches and the final (potentially partial word) fetch here
                     with m.If(additional_words_regd == 1):
@@ -227,22 +225,22 @@ class GoldenArbitraryWidthMemory(Elaboratable):
 
 
 
-class DummyPlug(Elaboratable):
 
-    #def __init__(self):
 
 
 
+class DummyPlug(Elaboratable):
+
     def elaborate(self, platform):
         m = Module()
 
-        m.submodules.FakeAWMem = FakeAWMem = ArbitraryWidthMemory(fake_data_width=7,
-                            fake_address_width=8, initial_data=[0xff,0xff, 0xff, 0xff, 0xff,0xff,0xff,],
+        m.submodules.FakeAWMem = FakeAWMem = ArbitraryWidthMemory(fake_data_width=4,
+                            fake_address_width=8, initial_data=[0xef,0xde, 0xaf, 0xec, 0xed,0xda,0xbe, 0xef],
                             backing_memory_data_width=8, backing_memory_address_width=8)
-        counter = Signal(8, reset=1)
+        counter = Signal(8, reset=0)
 
-#        with m.If(FakeAWMem.bus.ready_out == 1):
-            #m.d.sync += counter.eq(counter+1)
+        with m.If(FakeAWMem.bus.ready_out == 1):
+            m.d.sync += counter.eq(counter+1)
 
         #with m.If(counter == 4):
         m.d.comb += FakeAWMem.bus.valid_in.eq(1)