From 0e3cb2eb3e0bed8329a9946dc54f42101b0069b5 Mon Sep 17 00:00:00 2001
From: Kia <kia@special-circumstanc.es>
Date: Fri, 29 Jan 2021 19:41:08 -0700
Subject: [PATCH] refactor to use nmigen buses
---
unoptimized_lr/simple_lr_stack.py | 92 +++++++++++++++----------------
1 file changed, 46 insertions(+), 46 deletions(-)
diff --git a/unoptimized_lr/simple_lr_stack.py b/unoptimized_lr/simple_lr_stack.py
index 9f2b25d..e50e9b7 100644
--- a/unoptimized_lr/simple_lr_stack.py
+++ b/unoptimized_lr/simple_lr_stack.py
@@ -63,11 +63,11 @@ class ParseStack(Elaboratable):
self.bus = ParseStackBus(data_width = width, index_width=len(dummy_index), command_width=3)
- self.strobe = Signal(1) # replace this with valid_in
+ #self.strobe = Signal(1) # replace this with valid_in
# Data inputs
- self.in_data_port = Signal(width) # data_in
- self.in_aux_port = Signal(range(depth)) #Index_in
+ #self.in_data_port = Signal(width) # data_in
+ #self.in_aux_port = Signal(range(depth)) #Index_in
self.in_data_valid = Signal(1) # merge this and the one below, replace with valid_in
self.in_aux_valid = Signal(1) #
@@ -118,12 +118,12 @@ class ParseStack(Elaboratable):
with m.FSM() as fsm:
with m.State("EMPTY"):
- with m.If(self.strobe == 1):
- with m.Switch(self.command_port):
+ with m.If(self.bus.valid_in == 1):
+ with m.Switch(self.bus.command_in):
with m.Case(self.PUSH):
with m.If(self.in_data_valid == 1):
m.d.comb += wport.addr.eq(stack_pointer)
- m.d.comb += wport.data.eq(self.in_data_port)
+ m.d.comb += wport.data.eq(self.bus.data_in)
m.d.comb += wport.en.eq(1)
m.next = "AT_LEAST_ONE_ITEM"
with m.Case(self.POP):
@@ -143,13 +143,13 @@ class ParseStack(Elaboratable):
m.next = "FAULTED"
with m.State("AT_LEAST_ONE_ITEM"):
- with m.If(self.strobe == 1):
+ with m.If(self.bus.valid_in == 1):
with m.Switch(self.command_port):
with m.Case(self.PUSH):
with m.If(self.in_data_valid == 1):
m.d.sync += stack_pointer.eq(stack_pointer + 1)
m.d.comb += wport.addr.eq(stack_pointer + 1)
- m.d.comb += wport.data.eq(self.in_data_port)
+ m.d.comb += wport.data.eq(self.bus.data_in)
m.d.comb += wport.en.eq(1)
m.next = "AT_LEAST_ONE_ITEM"
with m.Case(self.POP):
@@ -164,23 +164,23 @@ class ParseStack(Elaboratable):
m.d.sync += stack_pointer.eq(stack_pointer - 1)
with m.Case(self.MULTIPOP):
with m.If(self.in_aux_valid == 1):
- with m.If((self.in_aux_port - 1 ) > stack_pointer):
+ with m.If((self.bus.index_in - 1 ) > stack_pointer):
m.d.comb += self.internal_fault.eq(1)
m.next = "FAULTED"
- with m.Elif(self.in_aux_port == stack_pointer):
+ with m.Elif(self.bus.index_in == stack_pointer):
m.d.sync += stack_pointer.eq(0)
m.next = "EMPTY"
- with m.Elif(self.in_aux_port < stack_pointer):
- m.d.sync += stack_pointer.eq(stack_pointer - self.in_aux_port)
+ with m.Elif(self.bus.index_in < stack_pointer):
+ m.d.sync += stack_pointer.eq(stack_pointer - self.bus.index_in)
m.next = "AT_LEAST_ONE_ITEM"
with m.Case(self.INTROSPECT):
with m.If(self.in_aux_valid):
- with m.If(self.in_aux_port > stack_pointer):
+ with m.If(self.bus.index_in > stack_pointer):
m.d.comb += self.internal_fault.eq(1)
m.next = "FAULTED"
with m.Else():
- m.d.comb += rport.addr.eq(self.in_aux_port)
+ m.d.comb += rport.addr.eq(self.bus.index_in)
m.d.comb += self.out_data_port.eq(rport.data)
m.d.comb += self.out_data_valid.eq(1)
m.next = "AT_LEAST_ONE_ITEM"
@@ -227,38 +227,38 @@ class DummyPlug(Elaboratable):
m.d.sync += counter.eq(counter+1)
with m.If(counter==1):
- m.d.comb += m.submodules.stack.strobe.eq(1)
- m.d.comb += m.submodules.stack.in_data_valid.eq(ParseStack.PUSH)
- m.d.comb += m.submodules.stack.in_data_port.eq(42)
-
-
- with m.If(counter==2):
- m.d.comb += m.submodules.stack.command_port.eq(ParseStack.PUSH)
- m.d.comb += m.submodules.stack.strobe.eq(1)
- m.d.comb += m.submodules.stack.in_data_valid.eq(1)
- m.d.comb += m.submodules.stack.in_data_port.eq(43)
-
- with m.If(counter==3):
- m.d.comb += m.submodules.stack.command_port.eq(ParseStack.PUSH)
- m.d.comb += m.submodules.stack.strobe.eq(1)
- m.d.comb += m.submodules.stack.in_data_valid.eq(1)
- m.d.comb += m.submodules.stack.in_data_port.eq(44)
-
- with m.If(counter==4):
- m.d.comb += m.submodules.stack.command_port.eq(ParseStack.POP)
- m.d.comb += m.submodules.stack.strobe.eq(1)
-
- with m.If(counter==5):
- m.d.comb += m.submodules.stack.command_port.eq(ParseStack.POP)
- m.d.comb += m.submodules.stack.strobe.eq(1)
-
-
- with m.If(counter==7):
- m.d.comb += m.submodules.stack.command_port.eq(ParseStack.POP)
- m.d.comb += m.submodules.stack.strobe.eq(1)
- with m.If(counter==9):
- m.d.comb += m.submodules.stack.command_port.eq(ParseStack.POP)
- m.d.comb += m.submodules.stack.strobe.eq(1)
+ m.d.comb += m.submodules.stack.bus.valid_in.eq(1)
+ m.d.comb += m.submodules.stack.bus.command_in.eq(ParseStack.PUSH)
+ m.d.comb += m.submodules.stack.bus.data_in.eq(42)
+
+
+ # with m.If(counter==2):
+ # m.d.comb += m.submodules.stack.command_port.eq(ParseStack.PUSH)
+ # m.d.comb += m.submodules.stack.strobe.eq(1)
+ # m.d.comb += m.submodules.stack.in_data_valid.eq(1)
+ # m.d.comb += m.submodules.stack.in_data_port.eq(43)
+
+ # with m.If(counter==3):
+ # m.d.comb += m.submodules.stack.command_port.eq(ParseStack.PUSH)
+ # m.d.comb += m.submodules.stack.strobe.eq(1)
+ # m.d.comb += m.submodules.stack.in_data_valid.eq(1)
+ # m.d.comb += m.submodules.stack.in_data_port.eq(44)
+
+ # with m.If(counter==4):
+ # m.d.comb += m.submodules.stack.command_port.eq(ParseStack.POP)
+ # m.d.comb += m.submodules.stack.strobe.eq(1)
+
+ # with m.If(counter==5):
+ # m.d.comb += m.submodules.stack.command_port.eq(ParseStack.POP)
+ # m.d.comb += m.submodules.stack.strobe.eq(1)
+
+
+ # with m.If(counter==7):
+ # m.d.comb += m.submodules.stack.command_port.eq(ParseStack.POP)
+ # m.d.comb += m.submodules.stack.strobe.eq(1)
+ # with m.If(counter==9):
+ # m.d.comb += m.submodules.stack.command_port.eq(ParseStack.POP)
+ # m.d.comb += m.submodules.stack.strobe.eq(1)
return m
--
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