diff --git a/gearbox.py b/gearbox.py
index 17c711bc1559adcd33adf2d2238069fa168047c6..fb3b65e5f45370df80d8217b0cd04d56f8c87bfc 100755
--- a/gearbox.py
+++ b/gearbox.py
@@ -40,10 +40,10 @@ class ArbitraryGearbox(Elaboratable):
             #storage   = Signal(len_storage, reset= 0b111_110_101_100_011_010_001)
 
 
-            storage   = Signal(len_storage, reset= 0b1_100_011_00)
+            storage   = Signal(len_storage)
 
             write_ptr = Signal(range(len_storage))
-            read_ptr  = Signal(range(len_storage), reset=2)
+            read_ptr  = Signal(range(len_storage))
 
             # read index logic here
             with m.If(read_ptr + self.out_width >= len_storage):
@@ -68,6 +68,24 @@ class ArbitraryGearbox(Elaboratable):
                                 ))
 
 
+            # The buffer is composed of two different flavor of bits:
+
+            # Invalid bits  CANNOT BE READ OUT     CAN BE WRITTEN TO
+            # Valid bits    CAN BE READ OUT        CANNOT BE WRITTEN TO
+
+            # and the location of those bits are given by the read_ptr and the write_ptr
+
+            # We only allow a read operation (which is not idempotent as the read_ptr is advanced) if:
+            # 1) the downstream interface is signaling ready
+            # 2) there are out_width valid bits in front of the read_ptr
+
+
+            # Likewise, we only allow a write operation (which is heavily non-idempotent as the write_ptr is advanced
+            # and the buffer is modified) if:
+            # 1) the upstream interface is signaling valid (we cannot allow ourselves to ingest invalid data!)
+            # 2) there are in_width invalid bits in front of the write_ptr
+
+
 
 
             return m