From 10d29e658926be81dfe879e1ab99c5fa4b8963be Mon Sep 17 00:00:00 2001
From: Kia <kia@special-circumstanc.es>
Date: Tue, 2 Feb 2021 17:16:52 -0700
Subject: [PATCH] explain logic for flow-control
---
gearbox.py | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/gearbox.py b/gearbox.py
index 17c711b..fb3b65e 100755
--- a/gearbox.py
+++ b/gearbox.py
@@ -40,10 +40,10 @@ class ArbitraryGearbox(Elaboratable):
#storage = Signal(len_storage, reset= 0b111_110_101_100_011_010_001)
- storage = Signal(len_storage, reset= 0b1_100_011_00)
+ storage = Signal(len_storage)
write_ptr = Signal(range(len_storage))
- read_ptr = Signal(range(len_storage), reset=2)
+ read_ptr = Signal(range(len_storage))
# read index logic here
with m.If(read_ptr + self.out_width >= len_storage):
@@ -68,6 +68,24 @@ class ArbitraryGearbox(Elaboratable):
))
+ # The buffer is composed of two different flavor of bits:
+
+ # Invalid bits CANNOT BE READ OUT CAN BE WRITTEN TO
+ # Valid bits CAN BE READ OUT CANNOT BE WRITTEN TO
+
+ # and the location of those bits are given by the read_ptr and the write_ptr
+
+ # We only allow a read operation (which is not idempotent as the read_ptr is advanced) if:
+ # 1) the downstream interface is signaling ready
+ # 2) there are out_width valid bits in front of the read_ptr
+
+
+ # Likewise, we only allow a write operation (which is heavily non-idempotent as the write_ptr is advanced
+ # and the buffer is modified) if:
+ # 1) the upstream interface is signaling valid (we cannot allow ourselves to ingest invalid data!)
+ # 2) there are in_width invalid bits in front of the write_ptr
+
+
return m
--
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