From 24d6c807f47116fdae464f664af45a795903b070 Mon Sep 17 00:00:00 2001
From: Kia <kia@special-circumstanc.es>
Date: Mon, 29 Mar 2021 16:12:43 -0600
Subject: [PATCH] remove superfluous asserts. at least i think they're
superfluous, we still need to check with different upstream/downstream
widths.
---
rtl_lib/gearbox.py | 14 ++------------
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/rtl_lib/gearbox.py b/rtl_lib/gearbox.py
index 27f72fd..a482f01 100644
--- a/rtl_lib/gearbox.py
+++ b/rtl_lib/gearbox.py
@@ -222,7 +222,7 @@ class DummyPlug(Elaboratable):
upstream_width = 1
downstream_width = 1
- sim_memory_size = 8
+ sim_memory_size = 64
expiration_date = int(sim_memory_size/upstream_width)-2
@@ -268,20 +268,12 @@ class DummyPlug(Elaboratable):
# no upstream transaction, no downstream transaction
m.d.comb += Assert(1==1)
- with m.If(Past(ResetSignal()) == 1):
- m.d.comb += Assert(0 == golden.fake_occupied)
- m.d.comb += Assert(gearbox.valid_bit_count == 0)
- m.d.comb += Assert(upstream_txn == 0)
- m.d.comb += Assert(downstream_txn == 0)
- #m.d.comb += Cover(ResetSignal() == 1)
-
-
-
valid_slice_gearbox = Signal(8)
slice_golden = Signal(8)
with m.If(wrapped == 0):
with m.Switch(gearbox.valid_bit_count):
+ # we need to handle the case where all bits in the shift reg are valid, so add that +1
for cand_valids in range(0, gearbox.shift_reg_len+1):
with m.Case(cand_valids):
m.d.comb += Assert(0 == gearbox.shift_reg.bit_select(cand_valids, gearbox.shift_reg_len-cand_valids))
@@ -297,8 +289,6 @@ class DummyPlug(Elaboratable):
m.d.comb += Assert(gearbox.bus.upstream_ready_out == golden.bus.upstream_ready_out)
m.d.comb += Assert(gearbox.bus.downstream_valid_out == golden.bus.downstream_valid_out)
- with m.If(gearbox.valid_bit_count == 0):
- m.d.comb += Assert(gearbox.shift_reg == 0)
#m.d.comb += Assert(gearbox.shift_reg.bit_select(0,gearbox.valid_bit_count) == 1)
with m.If(gearbox.bus.downstream_valid_out == 1):
--
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