diff --git a/combinatorial_LR_parser.py b/combinatorial_LR_parser.py
index f6557922b6eeba12fb3bcc74b6c48637eec3804a..9812f3c805c66978fa3fa63496d2a870827eec26 100644
--- a/combinatorial_LR_parser.py
+++ b/combinatorial_LR_parser.py
@@ -514,14 +514,14 @@ class MasterStateMachine(Elaboratable):
         # Skid buffer
         fsm_ready = Signal(1)
         fsm_data_valid = Signal(1)
-        fsm_data = Signal(self.item_width)
+        fsm_data_out = Signal(self.item_width)
 
 
         m.d.comb += skbuffer.upstream_valid_in.eq(self.data_in_valid)
         m.d.comb += self.data_in_ready.eq(skbuffer.upstream_ready_out)
         m.d.comb += skbuffer.upstream_data_in.eq(self.data_in)
         m.d.comb += skbuffer.downstream_ready_in.eq(fsm_ready)
-        m.d.comb += fsm_data.eq(skbuffer.downstream_data_out)
+        m.d.comb += fsm_data_out.eq(skbuffer.downstream_data_out)
         m.d.comb += fsm_data_valid.eq(skbuffer.downstream_valid_out)
 
 
@@ -533,7 +533,7 @@ class MasterStateMachine(Elaboratable):
                     with m.If(fsm_data_valid == 1):
                         m.d.comb += stack.command_in.eq(2)
                         m.d.comb += stack.command_in_strobe.eq(1)
-                        m.d.comb += stack.push_port.eq(fsm_data)
+                        m.d.comb += stack.push_port.eq(fsm_data_out)
                         m.d.comb += fsm_ready.eq(1)