diff --git a/rtl_lib/shift_testing.py b/rtl_lib/shift_testing.py
new file mode 100644
index 0000000000000000000000000000000000000000..76f5f2c1a66ea093fd3802559a60018e3b4b0787
--- /dev/null
+++ b/rtl_lib/shift_testing.py
@@ -0,0 +1,30 @@
+from enum import Enum
+from nmigen import *
+from nmigen.hdl.rec import *
+from nmigen.asserts import *
+from nmigen.cli import main
+
+class DummyPlug(Elaboratable):
+
+    #def __init__(self):
+
+
+
+    def elaborate(self, platform):
+        m = Module()
+        egg = Signal(8, reset=219)
+        foo = Signal(8)
+        # the "constant mask" idea lets us use a constant compile-time bitmask while still letting us lop off a variable number of bits
+
+        counter = Signal(8)
+        m.d.sync += counter.eq(counter+1)
+        m.d.sync += foo.eq(((egg<<counter)&0xff)>>counter)
+
+        return m
+
+
+
+if __name__ == '__main__':
+    baka =DummyPlug()
+    main(baka)
+    #platform.build(DummyPlug())