From 5fcc6ccd1cb24d5f22fc2483b76a3462d204a9b8 Mon Sep 17 00:00:00 2001
From: Kia <kia@special-circumstanc.es>
Date: Mon, 25 Jan 2021 19:47:34 -0700
Subject: [PATCH] likewise with LR-table
---
unoptimized_lr/simple_lr_table.py | 29 ++++++++++++-----------------
1 file changed, 12 insertions(+), 17 deletions(-)
diff --git a/unoptimized_lr/simple_lr_table.py b/unoptimized_lr/simple_lr_table.py
index 3bf7947..a9e0c6d 100644
--- a/unoptimized_lr/simple_lr_table.py
+++ b/unoptimized_lr/simple_lr_table.py
@@ -67,21 +67,16 @@ class LRTable(Elaboratable):
self.number_of_terminals = number_of_terminals
- # Interfaces
- # Input data:
- self.state_in = Signal(range(number_of_states))
- self.terminal_in = Signal(range(number_of_terminals))
-
- # Control
- self.in_valid = Signal(1)
-
- # Output data:
- self.table_entry_out = Signal(self.table_width)
+ dummy_row = Signal(range(number_of_states))
+ dummy_column = Signal(range(number_of_terminals))
+ # Interfaces
+ self.bus = TableBus(row_input_width=len(dummy_row),
+ column_input_width=len(dummy_column),
+ output_width=self.table_width)
+ # Interfaces
- # Output control
- self.table_entry_out_valid = Signal(1)
# Prepare the table for consumption
@@ -103,14 +98,14 @@ class LRTable(Elaboratable):
m.submodules.wport = wport = (self.mem).write_port()
- m.d.sync += self.table_entry_out_valid.eq(self.in_valid)
+ m.d.sync += self.bus.valid_out.eq(self.bus.valid_in)
# Now we calculate the address:
tgt_address = Signal(self.table_depth)
- m.d.comb += tgt_address.eq(self.state_in * self.number_of_terminals + self.terminal_in)
+ m.d.comb += tgt_address.eq(self.bus.row_idx * self.number_of_terminals + self.bus.col_idx)
m.d.comb += rport.addr.eq(tgt_address)
- m.d.comb += self.table_entry_out.eq((rport.data))
+ m.d.comb += self.bus.output_data.eq((rport.data))
return m
@@ -215,7 +210,7 @@ class DummyPlug(Elaboratable):
def elaborate(self, platform):
m = Module()
- m.submodules.table = table = GOTOtable(3,3,[[1,2,3],[4,5,6],[1,7,1]])
+ m.submodules.table = table = LRTable(3,3,3,[[1,2,3],[4,5,6],[1,9,1]])
counter = Signal(8)
m.d.sync += counter.eq(counter+1)
@@ -225,7 +220,7 @@ class DummyPlug(Elaboratable):
m.d.comb += table.bus.col_idx.eq(0)
with m.If(counter == 4):
m.d.comb += table.bus.valid_in.eq(1)
- m.d.comb += table.bus.row_idx.eq(0)
+ m.d.comb += table.bus.row_idx.eq(1)
m.d.comb += table.bus.col_idx.eq(1)
with m.If(counter == 6):
m.d.comb += table.bus.valid_in.eq(1)
--
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