diff --git a/unoptimized_lr/simple_lr_table.py b/unoptimized_lr/simple_lr_table.py
index 42fe5521ec0783f1edbfc7844184ac2bd83837f9..186f94e18f2764beae5f031fdd6dab75c98e05eb 100644
--- a/unoptimized_lr/simple_lr_table.py
+++ b/unoptimized_lr/simple_lr_table.py
@@ -31,21 +31,19 @@ class LRTable(Elaboratable):
         # This means that the length of each element has to be:
         # TIW = (2 bits + number of bits to index the reduce rules)
 
-        # Because this is not initially meant for synthesis efficiency, we
-        # initially just choose the width of the memory to be:
-
-        # width = number_of_terminals * TIW
+        # We choose the width of the memory to be the width of each element
 
         # and the depth to be:
-        # depth = number_of_states
+        # depth = number_of_states * number_of_terminals
 
         # We calculate these now:
 
         reduce_rule_signal = Signal(range(number_of_reduce_rules))
         reduce_rule_bits = len(reduce_rule_signal)
-        self.table_entry_width = (reduce_rule_bits + 2)
-        self.table_width = number_of_terminals * self.table_entry_width
-        self.table_depth = number_of_states
+        self.table_width = (reduce_rule_bits + 2)
+        self.table_depth = number_of_states * number_of_terminals
+
+        self.number_of_terminals = number_of_terminals
 
 
         # Interfaces
@@ -59,7 +57,7 @@ class LRTable(Elaboratable):
 
         # Output data:
 
-        self.table_entry_out = Signal(self.table_entry_width)
+        self.table_entry_out = Signal(self.table_width)
 
 
         # Output control
@@ -82,24 +80,16 @@ class LRTable(Elaboratable):
         m = Module()
         m.submodules.rport = rport = (self.mem).read_port()
         m.submodules.wport = wport = (self.mem).write_port()
-        row_address = Signal(self.table_depth)
-
-        m.d.comb += row_address.eq(self.state_in)
-        m.d.comb += rport.addr.eq(row_address)
 
 
         m.d.sync += self.table_entry_out_valid.eq(self.in_valid)
 
-        # Now we calculate the column address:
-
-        registered_column = Signal(len(self.terminal_in))
-
-        m.d.sync += registered_column.eq(self.terminal_in)
-
-
-        m.d.comb += self.table_entry_out.eq((rport.data).word_select(registered_column, self.table_entry_width))
-
+        # Now we calculate the address:
+        tgt_address = Signal(self.table_depth)
+        m.d.comb += tgt_address.eq(self.state_in * self.number_of_terminals + self.terminal_in)
+        m.d.comb += rport.addr.eq(tgt_address)
 
+        m.d.comb += self.table_entry_out.eq((rport.data))
 
         return m
 
@@ -143,9 +133,11 @@ class GOTOtable(Elaboratable):
 
         nonterminal_signal = Signal(range(number_of_nonterminals))
         nonterminal_bits = len(nonterminal_signal)
-        self.table_entry_width = (nonterminal_bits + 1)
-        self.table_width = number_of_nonterminals * self.table_entry_width
-        self.table_depth = number_of_states
+        self.table_width = (nonterminal_bits + 1)
+        print(number_of_nonterminals)
+        self.table_depth = number_of_nonterminals * number_of_states
+
+        self.number_of_nonterminals = number_of_nonterminals
 
 
         # Interfaces
@@ -159,7 +151,7 @@ class GOTOtable(Elaboratable):
 
         # Output data:
 
-        self.table_entry_out = Signal(self.table_entry_width)
+        self.table_entry_out = Signal(self.table_width)
 
 
         # Output control
@@ -183,22 +175,16 @@ class GOTOtable(Elaboratable):
         m = Module()
         m.submodules.rport = rport = (self.mem).read_port()
         m.submodules.wport = wport = (self.mem).write_port()
-        row_address = Signal(self.table_depth)
-
-        m.d.comb += row_address.eq(self.state_in)
-        m.d.comb += rport.addr.eq(row_address)
 
 
         m.d.sync += self.table_entry_out_valid.eq(self.in_valid)
 
-        # Now we calculate the column address:
-
-        registered_column = Signal(len(self.nonterminal_in))
-
-        m.d.sync += registered_column.eq(self.nonterminal_in)
+        # Now we calculate the address:
+        tgt_address = Signal(self.table_depth)
+        m.d.comb += tgt_address.eq(self.state_in * self.number_of_nonterminals + self.nonterminal_in)
+        m.d.comb += rport.addr.eq(tgt_address)
 
-
-        m.d.comb += self.table_entry_out.eq((rport.data).word_select(registered_column, self.table_entry_width))
+        m.d.comb += self.table_entry_out.eq((rport.data))
 
 
 
@@ -216,21 +202,22 @@ class DummyPlug(Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
-        m.submodules.table = table = GOTOtable(3,2,[[1,2],[3,4],[5,6]])
+        m.submodules.table = table = GOTOtable(3,3,[[1,2,3],[4,5,6],[7,0,1]])
         counter = Signal(8)
         m.d.sync += counter.eq(counter+1)
 
         with m.If(counter == 3):
             m.d.comb += table.in_valid.eq(1)
-            m.d.comb += table.state_in.eq(1)
-            m.d.comb += table.nonterminal_in.eq(1)
+            m.d.comb += table.state_in.eq(0)
+            m.d.comb += table.nonterminal_in.eq(0)
         with m.If(counter == 4):
-            m.d.comb += table.in_valid.eq(1)
-            m.d.comb += table.state_in.eq(2)
-        with m.If(counter == 6):
             m.d.comb += table.in_valid.eq(1)
             m.d.comb += table.state_in.eq(0)
             m.d.comb += table.nonterminal_in.eq(1)
+        with m.If(counter == 6):
+            m.d.comb += table.in_valid.eq(1)
+            m.d.comb += table.state_in.eq(2)
+            m.d.comb += table.nonterminal_in.eq(0)
         return m