From 6db9cb8cba166ce35ad7a54ec671801019cfb5e9 Mon Sep 17 00:00:00 2001
From: Kia <kia@special-circumstanc.es>
Date: Tue, 6 Apr 2021 11:27:43 -0600
Subject: [PATCH] take care of nonzero least-significant bit index
---
rtl_lib/arbitrary_width_memory.py | 7 +++----
rtl_lib/shift_testing.py | 21 +++++++++++++++------
2 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/rtl_lib/arbitrary_width_memory.py b/rtl_lib/arbitrary_width_memory.py
index 4e46f0c..456b40c 100644
--- a/rtl_lib/arbitrary_width_memory.py
+++ b/rtl_lib/arbitrary_width_memory.py
@@ -99,7 +99,7 @@ class ArbitraryWidthMemory(Elaboratable):
m.d.comb += self.bus.r_data.eq(read_port.data)
shreg = Signal(self.fake_data_width)
- current_slice = Signal(self.backing_memory_data_width)
+ current_slice = Signal(self.fake_data_width)
lower_bits_cut = Signal(self.backing_memory_data_width)
top_cut = Signal(range(self.backing_memory_data_width+1))
@@ -107,8 +107,7 @@ class ArbitraryWidthMemory(Elaboratable):
shreg_new_bits = Signal(range(self.backing_memory_data_width+1))
m.d.comb += lower_bits_cut.eq(read_port.data>>LS_bit_index)
- m.d.comb += top_cut.eq(self.backing_memory_data_width-MS_bit_index-1) #is this correct given there's the lower bit cutting that happens before this? we need to draw it out to be sure
- m.d.comb += current_slice.eq(((lower_bits_cut<<top_cut)&0xff)>>top_cut)
+ m.d.comb += top_cut.eq(self.backing_memory_data_width-MS_bit_index-1+LS_bit_index)
m.d.comb += shreg_new_bits.eq(MS_bit_index-LS_bit_index+1)
@@ -235,7 +234,7 @@ class DummyPlug(Elaboratable):
m = Module()
m.submodules.FakeAWMem = FakeAWMem = ArbitraryWidthMemory(fake_data_width=4,
- fake_address_width=8, initial_data=[0xef,0xde, 0xaf, 0xec, 0xed,0xda,0xbe, 0xef],
+ fake_address_width=8, initial_data=[0xAB,0xCD, 0xEF, 0x55, 0xab,0xcd,0xef, 0xaa],
backing_memory_data_width=8, backing_memory_address_width=8)
counter = Signal(8, reset=0)
diff --git a/rtl_lib/shift_testing.py b/rtl_lib/shift_testing.py
index 76f5f2c..0dff35a 100644
--- a/rtl_lib/shift_testing.py
+++ b/rtl_lib/shift_testing.py
@@ -12,13 +12,22 @@ class DummyPlug(Elaboratable):
def elaborate(self, platform):
m = Module()
- egg = Signal(8, reset=219)
- foo = Signal(8)
- # the "constant mask" idea lets us use a constant compile-time bitmask while still letting us lop off a variable number of bits
- counter = Signal(8)
- m.d.sync += counter.eq(counter+1)
- m.d.sync += foo.eq(((egg<<counter)&0xff)>>counter)
+ unsliced = Signal(8,reset=0b1111_1111)
+
+ current_slice = Signal(8)
+ lower_bits_cut = Signal(8)
+ top_cut = Signal(4)
+
+ LS_bit_index = Signal(4,reset=1)
+ MS_bit_index = Signal(4,reset=7)
+ m.d.sync += MS_bit_index.eq(MS_bit_index-1)
+
+ m.d.comb += lower_bits_cut.eq(unsliced>>LS_bit_index)
+ m.d.comb += top_cut.eq(8-MS_bit_index-1+LS_bit_index) #is this correct given there's the lower bit cutting that happens before this? we need to draw it out to be sure
+ m.d.comb += current_slice.eq(((lower_bits_cut<<top_cut)&0xff)>>top_cut)
+
+ #m.d.comb += shreg_new_bits.eq(MS_bit_index-LS_bit_index+1)
return m
--
GitLab