From 7851b840480aa49b520e3d4234dc872521080a05 Mon Sep 17 00:00:00 2001
From: Kia <kia@special-circumstanc.es>
Date: Thu, 11 Mar 2021 20:24:43 -0700
Subject: [PATCH] start arbitrary width memory HDL
---
arbitrary_width_memory.py | 110 ++++++++++++++++++++++++++++++++++++++
1 file changed, 110 insertions(+)
create mode 100644 arbitrary_width_memory.py
diff --git a/arbitrary_width_memory.py b/arbitrary_width_memory.py
new file mode 100644
index 0000000..2528c07
--- /dev/null
+++ b/arbitrary_width_memory.py
@@ -0,0 +1,110 @@
+from enum import Enum
+from nmigen import *
+from nmigen.hdl.rec import *
+from nmigen.asserts import *
+from nmigen.cli import main
+
+
+
+
+class ArbitraryWidthMemoryLayout(Layout):
+ def __init__(self, *, data_width, address_width): # the * forces keyword args
+ super().__init__([
+ # DATA
+ ("r_data", unsigned(data_width)), # OUTPUT
+ ("w_data", unsigned(data_width)), # INPUT
+
+ # ADDRESS
+ ("r_addr", unsigned(address_width)), # INPUT
+ ("w_addr", unsigned(address_width)), # INPUT
+
+
+ # CONTROL
+ ("fault", 1),
+
+ # MODE SELECT
+ ("write_enable", 1), # INPUT
+
+ # FLOW CONTROL UPSTREAM
+ ("valid_in", 1), # INPUT
+ ("ready_out", 1), # OUTPUT
+
+ # FLOW CONTROL DOWNSTREAM
+ ("valid_out", 1), # OUTPUT
+ ("ready_in", 1), # INPUT
+
+ ])
+
+class ArbitraryWidthMemoryBus(Record):
+ def __init__(self, *, data_width, address_width):
+ super().__init__(ArbitraryWidthMemoryLayout(data_width=data_width, address_width=address_width))
+
+
+
+class ArbitraryGearbox(Elaboratable):
+ def __init__(self, *, data_width, address_width):
+ self.data_width = data_width
+ self.address_width = address_width
+
+ self.bus = ArbitraryWidthMemoryBus(data_width=data_width, address_width=address_width)
+
+ def elaborate(self, platform):
+ m = Module()
+
+
+ return m
+
+
+
+# This is non-synthesizable but is intended to provide a model for formal verification.
+
+class GoldenAWModel(Elaboratable):
+ def __init__(self, *, in_width, out_width, sim_memory_size):
+ self.in_width = in_width
+ self.out_width = out_width
+ assert(in_width == out_width)
+
+ self.memory = Signal(sim_memory_size)
+
+ self.bus = ArbitraryWidthMemoryBus(in_width=in_width, out_width=out_width)
+
+ def elaborate(self, platform):
+
+
+ write_ptr = Signal(range(sim_memory_size))
+ read_ptr = Signal(range(sim_memory_size))
+
+
+ m = Module()
+ return m
+
+
+
+class DummyPlug(Elaboratable):
+
+ #def __init__(self):
+
+
+
+ def elaborate(self, platform):
+ m = Module()
+
+ m.submodules.gearbox = gearbox = IdempotentGearbox(in_width=(3), out_width=3)
+ #counter = Signal(8)
+ #m.d.sync += counter.eq(counter+1)
+
+# with m.If(counter == 3):
+# m.d.comb += gearbox.bus.valid_in.eq(1)
+ m.d.comb += gearbox.bus.data_in.eq(AnySeq(3))
+ m.d.comb += gearbox.bus.ready_in.eq(AnySeq(1))
+ m.d.comb += gearbox.bus.valid_in.eq(AnySeq(1))
+
+
+ return m
+
+
+
+if __name__ == '__main__':
+ baka =DummyPlug()
+ main(baka)
+ #platform.build(DummyPlug())
--
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