diff --git a/rtl_lib/arbitrary_width_memory.py b/rtl_lib/arbitrary_width_memory.py
index df9c789324bff70e18af87f13121fe37a63cc633..ed790ac496b9feab5acc9738384e08ac6ef00b73 100644
--- a/rtl_lib/arbitrary_width_memory.py
+++ b/rtl_lib/arbitrary_width_memory.py
@@ -126,7 +126,7 @@ class ArbitraryWidthMemory(Elaboratable):
 
                         # Here's where they start trying to trick you. We need to handle the case where the end of the
                         # fake word goes beyond a real memory word.
-                        m.d.comb += end_bit_pseudo_index.eq(left_bit_index + self.fake_data_width-1)
+                        m.d.comb += end_bit_pseudo_index.eq(left_bit_index + self.fake_data_width - 1)
 
                         # So here we determine if there's any need for additional memory words:
                         m.d.comb += additional_words.eq(end_bit_pseudo_index[self.backing_memory_data_width_bits:])
@@ -214,7 +214,7 @@ class DummyPlug(Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
-        m.submodules.FakeAWMem = FakeAWMem = ArbitraryWidthMemory(fake_data_width=16,
+        m.submodules.FakeAWMem = FakeAWMem = ArbitraryWidthMemory(fake_data_width=9,
                             fake_address_width=8, initial_data=[0x23,0x45, 0x67, 0x89, 0xab,0xcd,0xef],
                             backing_memory_data_width=8, backing_memory_address_width=8)
         counter = Signal(8, reset=1)