From 7bcd6406e8543a39417025e9a393501e37174318 Mon Sep 17 00:00:00 2001
From: Kia <kia@special-circumstanc.es>
Date: Fri, 2 Apr 2021 21:38:02 -0600
Subject: [PATCH] seems to work, i think we should write the shift register so
we can do the proof against the golden model (which uses a nonsynthesizable
RAM)
---
rtl_lib/arbitrary_width_memory.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/rtl_lib/arbitrary_width_memory.py b/rtl_lib/arbitrary_width_memory.py
index df9c789..ed790ac 100644
--- a/rtl_lib/arbitrary_width_memory.py
+++ b/rtl_lib/arbitrary_width_memory.py
@@ -126,7 +126,7 @@ class ArbitraryWidthMemory(Elaboratable):
# Here's where they start trying to trick you. We need to handle the case where the end of the
# fake word goes beyond a real memory word.
- m.d.comb += end_bit_pseudo_index.eq(left_bit_index + self.fake_data_width-1)
+ m.d.comb += end_bit_pseudo_index.eq(left_bit_index + self.fake_data_width - 1)
# So here we determine if there's any need for additional memory words:
m.d.comb += additional_words.eq(end_bit_pseudo_index[self.backing_memory_data_width_bits:])
@@ -214,7 +214,7 @@ class DummyPlug(Elaboratable):
def elaborate(self, platform):
m = Module()
- m.submodules.FakeAWMem = FakeAWMem = ArbitraryWidthMemory(fake_data_width=16,
+ m.submodules.FakeAWMem = FakeAWMem = ArbitraryWidthMemory(fake_data_width=9,
fake_address_width=8, initial_data=[0x23,0x45, 0x67, 0x89, 0xab,0xcd,0xef],
backing_memory_data_width=8, backing_memory_address_width=8)
counter = Signal(8, reset=1)
--
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