diff --git a/unoptimized_lr/simple_lr_stack.py b/unoptimized_lr/simple_lr_stack.py
index 976b296f050025160d9efec1894a23efd02df19b..577a5005acae08ff8a7a932d0c31b54c6aed8c2d 100644
--- a/unoptimized_lr/simple_lr_stack.py
+++ b/unoptimized_lr/simple_lr_stack.py
@@ -10,7 +10,8 @@ from skidbuffer import RegisteredSkidBuffer
 
 
 class StackLayout(Layout):
-    def __init__(self, *, data_width, index_width, command_width):
+    def __init__(self, *, data_width, index_width):
+        command_width = 3
         super().__init__([
             # INPUTS
             ("command_in",     unsigned(command_width)), # FROM SOURCE
@@ -29,8 +30,8 @@ class StackLayout(Layout):
         ])
 
 class StackBus(Record):
-    def __init__(self, *, data_width, index_width, command_width):
-        super().__init__(StackLayout(data_width=data_width, index_width=index_width, command_width=command_width))
+    def __init__(self, *, data_width, index_width):
+        super().__init__(StackLayout(data_width=data_width, index_width=index_width))
 
 class Stack(Elaboratable):
     PUSH = 0
@@ -61,7 +62,7 @@ class Stack(Elaboratable):
         # read stack pointer outputs the stack pointer on the aux port
         dummy_index = Signal(range(depth))
 
-        self.bus = StackBus(data_width = width, index_width=len(dummy_index), command_width=3)
+        self.bus = StackBus(data_width = width, index_width=len(dummy_index))
 
         self.mem = Memory(width=self.width, depth=self.depth)