diff --git a/rtl_lib/shift_testing.py b/rtl_lib/shift_testing.py
index 0dff35ad6cbb1cd59b918d3edd2d9db025a40942..16a9b470ef96434d2117d085f52e7a7d1ae2eaf9 100644
--- a/rtl_lib/shift_testing.py
+++ b/rtl_lib/shift_testing.py
@@ -1,5 +1,6 @@
 from enum import Enum
 from nmigen import *
+from nmigen.hdl.ast import *
 from nmigen.hdl.rec import *
 from nmigen.asserts import *
 from nmigen.cli import main
@@ -25,7 +26,8 @@ class DummyPlug(Elaboratable):
 
         m.d.comb += lower_bits_cut.eq(unsliced>>LS_bit_index)
         m.d.comb += top_cut.eq(8-MS_bit_index-1+LS_bit_index) #is this correct given there's the lower bit cutting that happens before this? we need to draw it out to be sure
-        m.d.comb += current_slice.eq(((lower_bits_cut<<top_cut)&0xff)>>top_cut)
+#        m.d.comb += current_slice.eq(((lower_bits_cut<<top_cut)&0xff)>>top_cut)
+        m.d.comb += current_slice.eq(Part(unsliced, offset=LS_bit_index, width=MS_bit_index))
 
         #m.d.comb += shreg_new_bits.eq(MS_bit_index-LS_bit_index+1)