From 8830f9e2ed3645fea86d4460e1942b318245d581 Mon Sep 17 00:00:00 2001
From: Kia <kia@special-circumstanc.es>
Date: Tue, 6 Apr 2021 16:57:27 -0600
Subject: [PATCH] test using the internal nMigen "Part" function from
nmigen.hdl.ast to see if we can do variable-width slicing but no alas it
fails
---
rtl_lib/shift_testing.py | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/rtl_lib/shift_testing.py b/rtl_lib/shift_testing.py
index 0dff35a..16a9b47 100644
--- a/rtl_lib/shift_testing.py
+++ b/rtl_lib/shift_testing.py
@@ -1,5 +1,6 @@
from enum import Enum
from nmigen import *
+from nmigen.hdl.ast import *
from nmigen.hdl.rec import *
from nmigen.asserts import *
from nmigen.cli import main
@@ -25,7 +26,8 @@ class DummyPlug(Elaboratable):
m.d.comb += lower_bits_cut.eq(unsliced>>LS_bit_index)
m.d.comb += top_cut.eq(8-MS_bit_index-1+LS_bit_index) #is this correct given there's the lower bit cutting that happens before this? we need to draw it out to be sure
- m.d.comb += current_slice.eq(((lower_bits_cut<<top_cut)&0xff)>>top_cut)
+# m.d.comb += current_slice.eq(((lower_bits_cut<<top_cut)&0xff)>>top_cut)
+ m.d.comb += current_slice.eq(Part(unsliced, offset=LS_bit_index, width=MS_bit_index))
#m.d.comb += shreg_new_bits.eq(MS_bit_index-LS_bit_index+1)
--
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