From 923ae3f6dd15cb5834b64d5cfd403e30f89da985 Mon Sep 17 00:00:00 2001
From: Kia <kia@special-circumstanc.es>
Date: Mon, 25 Jan 2021 21:23:31 -0700
Subject: [PATCH] work on making it use the bus/layout/record/whatever
---
unoptimized_lr/simple_lr_stack.py | 47 +++++++++++++++++++++++--------
1 file changed, 36 insertions(+), 11 deletions(-)
diff --git a/unoptimized_lr/simple_lr_stack.py b/unoptimized_lr/simple_lr_stack.py
index 372a3d7..9f2b25d 100644
--- a/unoptimized_lr/simple_lr_stack.py
+++ b/unoptimized_lr/simple_lr_stack.py
@@ -1,13 +1,35 @@
from nmigen import *
from nmigen.hdl.rec import *
from nmigen.cli import main
+#from nmigen.utils import log2_int
from functools import reduce
from skidbuffer import RegisteredSkidBuffer
-
+class ParseStackLayout(Layout):
+ def __init__(self, *, data_width, index_width, command_width):
+ super().__init__([
+ # INPUTS
+ ("command_in", unsigned(command_width)), # FROM SOURCE
+ ("data_in", unsigned(data_width)), # FROM SOURCE
+ ("index_in", unsigned(index_width)), # FROM SOURCE
+ ("valid_in", 1), # FROM SOURCE
+ ("ready_in", 1), # FROM DEST
+
+ # OUTPUTS
+ ("data_out", unsigned(data_width)), # TO DEST
+ ("index_out", unsigned(index_width)), # TO DEST
+ ("valid_out", 1), # TO DEST
+ ("internal_fault", 1), # TO DEST
+ ("ready_out", 1), # TO SOURCE
+
+ ])
+
+class ParseStackBus(Record):
+ def __init__(self, *, data_width, index_width, command_width):
+ super().__init__(ParseStackLayout(data_width=data_width, index_width=index_width, command_width=command_width))
class ParseStack(Elaboratable):
PUSH = 0
@@ -37,24 +59,27 @@ class ParseStack(Elaboratable):
# on the output data port
# read stack pointer outputs the stack pointer on the aux port
+ dummy_index = Signal(range(depth))
+
+ self.bus = ParseStackBus(data_width = width, index_width=len(dummy_index), command_width=3)
- self.strobe = Signal(1) # when 1, execute the command
+ self.strobe = Signal(1) # replace this with valid_in
# Data inputs
- self.in_data_port = Signal(width)
- self.in_aux_port = Signal(range(depth))
- self.in_data_valid = Signal(1)
- self.in_aux_valid = Signal(1)
+ self.in_data_port = Signal(width) # data_in
+ self.in_aux_port = Signal(range(depth)) #Index_in
+ self.in_data_valid = Signal(1) # merge this and the one below, replace with valid_in
+ self.in_aux_valid = Signal(1) #
# Control outputs
- self.internal_fault = Signal(1)
+ self.internal_fault = Signal(1) # keep
# Data outputs
- self.out_data_port = Signal(width)
- self.out_aux_port = Signal(range(depth))
- self.out_data_valid = Signal(1)
- self.out_aux_valid = Signal(1)
+ self.out_data_port = Signal(width) #data_out
+ self.out_aux_port = Signal(range(depth)) # index_out
+ self.out_data_valid = Signal(1) # merge these as valid_out
+ self.out_aux_valid = Signal(1)#
self.mem = Memory(width=self.width, depth=self.depth)
--
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