diff --git a/lr_automaton_gateware.py b/lr_automaton_gateware.py
index c70d3a160ee508a6d090953dd21a4b01fc063a3f..717099be324ade6980f3aa1b566d0e96113fd169 100644
--- a/lr_automaton_gateware.py
+++ b/lr_automaton_gateware.py
@@ -42,16 +42,19 @@ class ParseStack(Elaboratable):
# Data inputs
self.in_data_port = Signal(width)
self.in_aux_port = Signal(range(depth))
- self.in_valid = Signal(1)
+ self.in_data_valid = Signal(1)
+ self.in_aux_valid = Signal(1)
+
# Control outputs
- self.valid_out = Signal(1)
self.internal_fault = Signal(1)
# Data outputs
self.out_data_port = Signal(width)
self.out_aux_port = Signal(range(depth))
self.out_data_valid = Signal(1)
+ self.out_aux_valid = Signal(1)
+
self.mem = Memory(width=self.width, depth=self.depth)
@@ -87,14 +90,12 @@ class ParseStack(Elaboratable):
bottom_of_stack_valid = Signal(1)
- multipop_left = Signal(range(self.depth))
-
with m.FSM() as fsm:
with m.State("EMPTY"):
with m.If(self.strobe == 1):
with m.Switch(self.command_port):
with m.Case(self.PUSH):
- with m.If(self.in_valid == 1):
+ with m.If(self.in_data_valid == 1):
m.d.comb += wport.addr.eq(stack_pointer)
m.d.comb += wport.data.eq(self.in_data_port)
m.d.comb += wport.en.eq(1)
@@ -119,7 +120,7 @@ class ParseStack(Elaboratable):
with m.If(self.strobe == 1):
with m.Switch(self.command_port):
with m.Case(self.PUSH):
- with m.If(self.in_valid == 1):
+ with m.If(self.in_data_valid == 1):
m.d.sync += stack_pointer.eq(stack_pointer + 1)
m.d.comb += wport.addr.eq(stack_pointer + 1)
m.d.comb += wport.data.eq(self.in_data_port)
@@ -128,6 +129,7 @@ class ParseStack(Elaboratable):
with m.Case(self.POP):
m.d.comb += rport.addr.eq(stack_pointer)
m.d.comb += self.out_data_port.eq(rport.data)
+ m.d.comb += self.out_data_valid.eq(1)
with m.If(stack_pointer == 0):
m.next = "EMPTY"
@@ -135,17 +137,40 @@ class ParseStack(Elaboratable):
m.next = "AT_LEAST_ONE_ITEM"
m.d.sync += stack_pointer.eq(stack_pointer - 1)
with m.Case(self.MULTIPOP):
- m.d.comb += self.internal_fault.eq(1)
- m.next = "FAULTED"
+ with m.If(self.in_aux_valid == 1):
+ with m.If((self.in_aux_port - 1 ) > stack_pointer):
+ m.d.comb += self.internal_fault.eq(1)
+ m.next = "FAULTED"
+ with m.Elif(self.in_aux_port == stack_pointer):
+ m.d.sync += stack_pointer.eq(0)
+ m.next = "EMPTY"
+ with m.Elif(self.in_aux_port < stack_pointer):
+ m.d.sync += stack_pointer.eq(stack_pointer - self.in_aux_port)
+ m.next = "AT_LEAST_ONE_ITEM"
+
with m.Case(self.INTROSPECT):
- m.d.comb += self.internal_fault.eq(1)
- m.next = "FAULTED"
+ with m.If(self.in_aux_valid):
+ with m.If(self.in_aux_port > stack_pointer):
+ m.d.comb += self.internal_fault.eq(1)
+ m.next = "FAULTED"
+ with m.Else():
+ m.d.comb += rport.addr.eq(self.in_aux_port)
+ m.d.comb += self.out_data_port.eq(rport.data)
+ m.d.comb += self.out_data_valid.eq(1)
+ m.next = "AT_LEAST_ONE_ITEM"
+
with m.Case(self.READ_TOS):
- m.d.comb += self.internal_fault.eq(1)
- m.next = "FAULTED"
+ m.d.comb += self.out_data_valid.eq(1)
+ m.d.comb += rport.addr.eq(stack_pointer)
+ m.d.comb += self.out_data_port.eq(rport.data)
+ m.d.comb += self.out_data_valid.eq(1)
+ m.next = "AT_LEAST_ONE_ITEM"
+
with m.Case(self.READ_SP):
- m.d.comb += self.internal_fault.eq(1)
- m.next = "FAULTED"
+ m.d.comb += self.out_aux_port.eq(stack_pointer)
+ m.d.comb += self.out_aux_valid.eq(1)
+ m.next = "AT_LEAST_ONE_ITEM"
+
with m.State("FAULTED"):
m.d.comb += self.internal_fault.eq(1)
m.next = "FAULTED"
@@ -177,20 +202,20 @@ class DummyPlug(Elaboratable):
with m.If(counter==1):
m.d.comb += m.submodules.stack.strobe.eq(1)
- m.d.comb += m.submodules.stack.in_valid.eq(1)
+ m.d.comb += m.submodules.stack.in_data_valid.eq(1)
m.d.comb += m.submodules.stack.in_data_port.eq(42)
with m.If(counter==2):
m.d.comb += m.submodules.stack.command_port.eq(0)
m.d.comb += m.submodules.stack.strobe.eq(1)
- m.d.comb += m.submodules.stack.in_valid.eq(1)
+ m.d.comb += m.submodules.stack.in_data_valid.eq(1)
m.d.comb += m.submodules.stack.in_data_port.eq(43)
with m.If(counter==3):
m.d.comb += m.submodules.stack.command_port.eq(0)
m.d.comb += m.submodules.stack.strobe.eq(1)
- m.d.comb += m.submodules.stack.in_valid.eq(1)
+ m.d.comb += m.submodules.stack.in_data_valid.eq(1)
m.d.comb += m.submodules.stack.in_data_port.eq(44)
with m.If(counter==4):
@@ -202,10 +227,10 @@ class DummyPlug(Elaboratable):
m.d.comb += m.submodules.stack.strobe.eq(1)
- with m.If(counter==6):
+ with m.If(counter==7):
m.d.comb += m.submodules.stack.command_port.eq(1)
m.d.comb += m.submodules.stack.strobe.eq(1)
- with m.If(counter==7):
+ with m.If(counter==9):
m.d.comb += m.submodules.stack.command_port.eq(1)
m.d.comb += m.submodules.stack.strobe.eq(1)
return m