From a4ae0282f8341796917af04f5c5c163d43c7ffa7 Mon Sep 17 00:00:00 2001
From: Kia <kia@special-circumstanc.es>
Date: Fri, 6 Dec 2019 21:06:05 -0700
Subject: [PATCH] continue work on skid buffer
---
skidbuffer.py | 33 ++++++++++++++++++++++++++-------
1 file changed, 26 insertions(+), 7 deletions(-)
diff --git a/skidbuffer.py b/skidbuffer.py
index a9eaee8..98afac1 100644
--- a/skidbuffer.py
+++ b/skidbuffer.py
@@ -1,15 +1,11 @@
from nmigen import *
from nmigen.cli import main
-from nmigen_boards.ice40_hx8k_b_evn import *
-
-from functools import reduce
-
class SkidBuffer(Elaboratable):
def __init__(self, width, registered):
self.width = width
- self.registered = registered
+ self.registered = registered # 1 if there's a register (delay) stage from input to output
self.upstream_valid_in = Signal(1)
self.upstream_ready_out = Signal(1)
@@ -22,5 +18,28 @@ class SkidBuffer(Elaboratable):
def elaborate(self, platform):
m = Module()
- skid_filled = Signal(1)
- skid_buffer = Signal(self.width)
\ No newline at end of file
+ skid_buffer = Signal(self.width)
+ skid_valid = Signal(1)
+
+
+
+ # we signal ready to upstream if and only if the skid buffer is empty
+
+ m.d.sync += upstream_ready_out.eq(~skid_valid)
+
+
+ # should we capture a value in the skid buffer?
+ # we should if upstream has data for us *and* downstream cannot accept
+
+ # If we want to fill our skid buffer, we need four conditions:
+ # 1. valid input data (upstream_valid_in == 1)
+ # 2. a buffer that is empty (upstream_ready_out == 1)
+ # 3. stalled downstream (downstream_ready_in == 0)
+ # 4.
+ with m.If((upstream_valid_in & upstream_ready_out) & (downstream_valid_out & ~(downstream_ready_in))):
+ m.d.sync += skid_valid.eq(1)
+
+ with m.If(downstream_ready_in == 1):
+ m.d.sync += skid_valid.eq(0)
+
+
--
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