diff --git a/rtl_lib/arbitrary_width_memory.py b/rtl_lib/arbitrary_width_memory.py
index 16bf2a3806e1a05820e30821b55709e98b6c1d98..f249ce714d491a3f6ef76e45cdea7159795d6122 100644
--- a/rtl_lib/arbitrary_width_memory.py
+++ b/rtl_lib/arbitrary_width_memory.py
@@ -9,8 +9,6 @@ from nmigen.cli import main
 # Signal(range(8)) will generate a THREE(3) wide signal, not enough to store 8
 # we need to check all our widths to verify we haven't fallen prey to this
 
-# we need to harmonize the terminology of "left" and "right" with LSB and MSB type terminology
-
 
 class ArbitraryWidthMemoryLayout(Layout):
     def __init__(self, *, data_width, address_width): # the * forces keyword args