From a752a05751389b20d1e108bc7097e954da303a3a Mon Sep 17 00:00:00 2001
From: Kia <kia@special-circumstanc.es>
Date: Sun, 4 Apr 2021 20:32:03 -0600
Subject: [PATCH] right/left terminology removed
---
rtl_lib/arbitrary_width_memory.py | 2 --
1 file changed, 2 deletions(-)
diff --git a/rtl_lib/arbitrary_width_memory.py b/rtl_lib/arbitrary_width_memory.py
index 16bf2a3..f249ce7 100644
--- a/rtl_lib/arbitrary_width_memory.py
+++ b/rtl_lib/arbitrary_width_memory.py
@@ -9,8 +9,6 @@ from nmigen.cli import main
# Signal(range(8)) will generate a THREE(3) wide signal, not enough to store 8
# we need to check all our widths to verify we haven't fallen prey to this
-# we need to harmonize the terminology of "left" and "right" with LSB and MSB type terminology
-
class ArbitraryWidthMemoryLayout(Layout):
def __init__(self, *, data_width, address_width): # the * forces keyword args
--
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