diff --git a/unoptimized_lr/simple_lr_stack.py b/unoptimized_lr/simple_lr_stack.py
index a8e5bff8e837eeaa000bc97c61baf61f370cbf74..976b296f050025160d9efec1894a23efd02df19b 100644
--- a/unoptimized_lr/simple_lr_stack.py
+++ b/unoptimized_lr/simple_lr_stack.py
@@ -8,7 +8,8 @@ from functools import reduce
 
 from skidbuffer import RegisteredSkidBuffer
 
-class ParseStackLayout(Layout):
+
+class StackLayout(Layout):
     def __init__(self, *, data_width, index_width, command_width):
         super().__init__([
             # INPUTS
@@ -27,11 +28,11 @@ class ParseStackLayout(Layout):
 
         ])
 
-class ParseStackBus(Record):
+class StackBus(Record):
     def __init__(self, *, data_width, index_width, command_width):
-        super().__init__(ParseStackLayout(data_width=data_width, index_width=index_width, command_width=command_width))
+        super().__init__(StackLayout(data_width=data_width, index_width=index_width, command_width=command_width))
 
-class ParseStack(Elaboratable):
+class Stack(Elaboratable):
     PUSH = 0
     POP  = 1
     MULTIPOP = 2
@@ -60,7 +61,7 @@ class ParseStack(Elaboratable):
         # read stack pointer outputs the stack pointer on the aux port
         dummy_index = Signal(range(depth))
 
-        self.bus = ParseStackBus(data_width = width, index_width=len(dummy_index), command_width=3)
+        self.bus = StackBus(data_width = width, index_width=len(dummy_index), command_width=3)
 
         self.mem = Memory(width=self.width, depth=self.depth)
 
@@ -193,42 +194,42 @@ class DummyPlug(Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
-        m.submodules.stack = ParseStack(8,8)
+        m.submodules.stack = Stack(8,8)
         counter = Signal(8)
         m.d.sync += counter.eq(counter+1)
 
         with m.If(counter==1):
             m.d.comb += m.submodules.stack.bus.valid_in.eq(1)
-            m.d.comb += m.submodules.stack.bus.command_in.eq(ParseStack.PUSH)
+            m.d.comb += m.submodules.stack.bus.command_in.eq(Stack.PUSH)
             m.d.comb += m.submodules.stack.bus.data_in.eq(42)
 
 
         with m.If(counter==2):
-            m.d.comb += m.submodules.stack.bus.command_in.eq(ParseStack.PUSH)
+            m.d.comb += m.submodules.stack.bus.command_in.eq(Stack.PUSH)
             m.d.comb += m.submodules.stack.bus.valid_in.eq(1)
             m.d.comb += m.submodules.stack.bus.data_in.eq(43)
 
         with m.If(counter==3):
-            m.d.comb += m.submodules.stack.bus.command_in.eq(ParseStack.PUSH)
+            m.d.comb += m.submodules.stack.bus.command_in.eq(Stack.PUSH)
             m.d.comb += m.submodules.stack.bus.valid_in.eq(1)
             m.d.comb += m.submodules.stack.bus.data_in.eq(44)
 
         with m.If(counter==4):
-            m.d.comb += m.submodules.stack.bus.command_in.eq(ParseStack.PUSH)
+            m.d.comb += m.submodules.stack.bus.command_in.eq(Stack.PUSH)
             m.d.comb += m.submodules.stack.bus.valid_in.eq(1)
             m.d.comb += m.submodules.stack.bus.data_in.eq(69)
 
 
         with m.If(counter==5):
-            m.d.comb += m.submodules.stack.bus.command_in.eq(ParseStack.POP)
+            m.d.comb += m.submodules.stack.bus.command_in.eq(Stack.POP)
             m.d.comb += m.submodules.stack.bus.valid_in.eq(1)
 
 
         with m.If(counter==7):
-            m.d.comb += m.submodules.stack.bus.command_in.eq(ParseStack.POP)
+            m.d.comb += m.submodules.stack.bus.command_in.eq(Stack.POP)
             m.d.comb += m.submodules.stack.bus.valid_in.eq(1)
         with m.If(counter==9):
-            m.d.comb += m.submodules.stack.bus.command_in.eq(ParseStack.POP)
+            m.d.comb += m.submodules.stack.bus.command_in.eq(Stack.POP)
             m.d.comb += m.submodules.stack.bus.valid_in.eq(1)
         return m