diff --git a/rtl_lib/arbitrary_width_memory.py b/rtl_lib/arbitrary_width_memory.py
index e25798c1e41c60b2366bfb245d5d39e40c3ac2cd..12253fe5b6056b1be3926e50b4d0c322bfe0561b 100644
--- a/rtl_lib/arbitrary_width_memory.py
+++ b/rtl_lib/arbitrary_width_memory.py
@@ -140,6 +140,7 @@ class ArbitraryWidthMemory(Elaboratable):
 
             m.d.comb += lower_bits_cut.eq(read_port.data>>LS_bit_index)
             m.d.comb += top_cut.eq(self.backing_memory_data_width-MS_bit_index-1+LS_bit_index)
+            m.d.comb += current_slice.eq(((lower_bits_cut<<top_cut)&0xff)>>top_cut)
 
             m.d.comb += shreg_new_bits.eq(MS_bit_index-LS_bit_index+1)
 
@@ -266,7 +267,7 @@ class DummyPlug(Elaboratable):
         m = Module()
 
         m.submodules.FakeAWMem = FakeAWMem = ArbitraryWidthMemory(fake_data_width=4,
-                            fake_address_width=8, initial_data=[0xAB,0xCD, 0xEF, 0x55, 0xab,0xcd,0xef, 0xaa],
+                            fake_address_width=8, initial_data=refolder([10,9,8,7,6,5,4,3,2,1],4, 8),
                             backing_memory_data_width=8, backing_memory_address_width=8)
         counter = Signal(8, reset=0)