From bada5a352f2d7b139cf8f9560a2995729f0567a6 Mon Sep 17 00:00:00 2001
From: Kia <kia@special-circumstanc.es>
Date: Tue, 6 Apr 2021 13:06:36 -0600
Subject: [PATCH] restore omitted line, use the refolder to initialize the
memory
---
rtl_lib/arbitrary_width_memory.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/rtl_lib/arbitrary_width_memory.py b/rtl_lib/arbitrary_width_memory.py
index e25798c..12253fe 100644
--- a/rtl_lib/arbitrary_width_memory.py
+++ b/rtl_lib/arbitrary_width_memory.py
@@ -140,6 +140,7 @@ class ArbitraryWidthMemory(Elaboratable):
m.d.comb += lower_bits_cut.eq(read_port.data>>LS_bit_index)
m.d.comb += top_cut.eq(self.backing_memory_data_width-MS_bit_index-1+LS_bit_index)
+ m.d.comb += current_slice.eq(((lower_bits_cut<<top_cut)&0xff)>>top_cut)
m.d.comb += shreg_new_bits.eq(MS_bit_index-LS_bit_index+1)
@@ -266,7 +267,7 @@ class DummyPlug(Elaboratable):
m = Module()
m.submodules.FakeAWMem = FakeAWMem = ArbitraryWidthMemory(fake_data_width=4,
- fake_address_width=8, initial_data=[0xAB,0xCD, 0xEF, 0x55, 0xab,0xcd,0xef, 0xaa],
+ fake_address_width=8, initial_data=refolder([10,9,8,7,6,5,4,3,2,1],4, 8),
backing_memory_data_width=8, backing_memory_address_width=8)
counter = Signal(8, reset=0)
--
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