From bf56d41e3e8457603309ec760045149f3fa946da Mon Sep 17 00:00:00 2001
From: Kia <kia@special-circumstanc.es>
Date: Wed, 24 Mar 2021 12:02:09 -0600
Subject: [PATCH] change parameters around a bit
---
rtl_lib/arbitrary_width_memory.py | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/rtl_lib/arbitrary_width_memory.py b/rtl_lib/arbitrary_width_memory.py
index 24aab10..001849c 100644
--- a/rtl_lib/arbitrary_width_memory.py
+++ b/rtl_lib/arbitrary_width_memory.py
@@ -59,11 +59,11 @@ class ArbitraryWidthMemory(Elaboratable):
# This is non-synthesizable but is intended to provide a model for formal verification.
class GoldenArbitraryWidthMemory(Elaboratable):
- def __init__(self, *, data_width, address_width, sim_memory_size):
+ def __init__(self, *, data_width, address_width, sim_memory):
self.data_width = data_width
self.address_width = address_width
- self.sim_memory_size = sim_memory_size
- self.memory = Memory(width=data_width, depth=sim_memory_size, init=[0x40,0x41,0x42, 0x43, 0x44, 0x45,0x46,0x47])
+ self.sim_memory_size = len(sim_memory)
+ self.memory = Memory(width=data_width, depth=self.sim_memory_size, init=sim_memory)
self.bus = ArbitraryWidthMemoryBus(data_width=data_width, address_width=address_width)
@@ -102,14 +102,14 @@ class DummyPlug(Elaboratable):
def elaborate(self, platform):
m = Module()
- m.submodules.AWMem = AWMem = GoldenArbitraryWidthMemory(data_width=7, address_width=8, sim_memory_size=8)
+ m.submodules.AWMem = AWMem = GoldenArbitraryWidthMemory(data_width=7, address_width=8, sim_memory=[0x40,0x41,0x42, 0x43, 0x44, 0x45,0x46,0x47])
counter = Signal(8)
m.d.sync += counter.eq(counter+1)
- with m.If(counter == 4):
- m.d.comb += AWMem.bus.valid_in.eq(1)
+ #with m.If(counter == 4):
+ m.d.comb += AWMem.bus.valid_in.eq(1)
m.d.comb += AWMem.bus.write_enable.eq(0)
m.d.comb += AWMem.bus.r_addr.eq(counter)
#m.d.comb += AWMem.bus.w_addr.eq(counter)
--
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