From c3e2389532d21216d6c3f50d9b0029ae4b585ded Mon Sep 17 00:00:00 2001
From: Kia <kia@special-circumstanc.es>
Date: Sat, 13 Mar 2021 15:13:31 -0700
Subject: [PATCH] arbitrary_width_memory.py
---
arbitrary_width_memory.py | 58 +++++++++++++++++++++++++--------------
1 file changed, 37 insertions(+), 21 deletions(-)
diff --git a/arbitrary_width_memory.py b/arbitrary_width_memory.py
index 2528c07..24aab10 100644
--- a/arbitrary_width_memory.py
+++ b/arbitrary_width_memory.py
@@ -41,12 +41,12 @@ class ArbitraryWidthMemoryBus(Record):
-class ArbitraryGearbox(Elaboratable):
+class ArbitraryWidthMemory(Elaboratable):
def __init__(self, *, data_width, address_width):
self.data_width = data_width
self.address_width = address_width
- self.bus = ArbitraryWidthMemoryBus(data_width=data_width, address_width=address_width)
+ self.bus = ArbitraryWidthMemoryBus(data_width=data_width, address_width=data_width)
def elaborate(self, platform):
m = Module()
@@ -58,24 +58,37 @@ class ArbitraryGearbox(Elaboratable):
# This is non-synthesizable but is intended to provide a model for formal verification.
-class GoldenAWModel(Elaboratable):
- def __init__(self, *, in_width, out_width, sim_memory_size):
- self.in_width = in_width
- self.out_width = out_width
- assert(in_width == out_width)
-
- self.memory = Signal(sim_memory_size)
+class GoldenArbitraryWidthMemory(Elaboratable):
+ def __init__(self, *, data_width, address_width, sim_memory_size):
+ self.data_width = data_width
+ self.address_width = address_width
+ self.sim_memory_size = sim_memory_size
+ self.memory = Memory(width=data_width, depth=sim_memory_size, init=[0x40,0x41,0x42, 0x43, 0x44, 0x45,0x46,0x47])
- self.bus = ArbitraryWidthMemoryBus(in_width=in_width, out_width=out_width)
+ self.bus = ArbitraryWidthMemoryBus(data_width=data_width, address_width=address_width)
def elaborate(self, platform):
+ m = Module()
+ write_ptr = Signal(range(self.sim_memory_size))
+ read_ptr = Signal(range(self.sim_memory_size))
- write_ptr = Signal(range(sim_memory_size))
- read_ptr = Signal(range(sim_memory_size))
+ m.submodules.read_port = read_port = self.memory.read_port()
+ m.submodules.write_port = write_port = self.memory.write_port()
+ bus = self.bus
+
+ with m.If(bus.valid_in == 1):
+ with m.If(bus.write_enable == 1):
+ m.d.comb += write_port.en.eq(1)
+ m.d.comb += write_port.addr.eq(bus.w_addr)
+ m.d.comb += write_port.data.eq(bus.w_data)
+ with m.Else():
+ #m.d.comb += read_port.en.eq(0)
+ m.d.comb += read_port.addr.eq(bus.r_addr)
+ m.d.comb += bus.r_data.eq(read_port.data)
+ m.d.sync += bus.valid_out.eq(1)
- m = Module()
return m
@@ -89,15 +102,18 @@ class DummyPlug(Elaboratable):
def elaborate(self, platform):
m = Module()
- m.submodules.gearbox = gearbox = IdempotentGearbox(in_width=(3), out_width=3)
- #counter = Signal(8)
- #m.d.sync += counter.eq(counter+1)
+ m.submodules.AWMem = AWMem = GoldenArbitraryWidthMemory(data_width=7, address_width=8, sim_memory_size=8)
+ counter = Signal(8)
+
+
+ m.d.sync += counter.eq(counter+1)
-# with m.If(counter == 3):
-# m.d.comb += gearbox.bus.valid_in.eq(1)
- m.d.comb += gearbox.bus.data_in.eq(AnySeq(3))
- m.d.comb += gearbox.bus.ready_in.eq(AnySeq(1))
- m.d.comb += gearbox.bus.valid_in.eq(AnySeq(1))
+ with m.If(counter == 4):
+ m.d.comb += AWMem.bus.valid_in.eq(1)
+ m.d.comb += AWMem.bus.write_enable.eq(0)
+ m.d.comb += AWMem.bus.r_addr.eq(counter)
+ #m.d.comb += AWMem.bus.w_addr.eq(counter)
+ #m.d.comb += AWMem.bus.w_data.eq(counter)
return m
--
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