diff --git a/rtl_lib/arbitrary_width_memory.py b/unoptimized_lr/rtl_lib/arbitrary_width_memory.py
similarity index 83%
rename from rtl_lib/arbitrary_width_memory.py
rename to unoptimized_lr/rtl_lib/arbitrary_width_memory.py
index 680fef1f5eb517f06f8f0ceea514da4cb15678ef..ec8ac1a881b805cb9c8114273dec7ae3033b72f6 100644
--- a/rtl_lib/arbitrary_width_memory.py
+++ b/unoptimized_lr/rtl_lib/arbitrary_width_memory.py
@@ -37,8 +37,25 @@ class ArbitraryWidthMemoryBus(Record):
+def folder(unwrapped_bits, *, desired_width):
+ surplus = len(unwrapped_bits) % desired_width
-def refolder(fake_array, fake_width, desired_width):
+ if (surplus != 0):
+ padding = desired_width - surplus
+ print("Padding", padding)
+ unwrapped_bits.extend(zeros(padding))
+
+ assert(len(unwrapped_bits) % desired_width == 0)
+
+ rewrapped_array = []
+
+ for idx in range(len(unwrapped_bits)//desired_width):
+ #print("slicer", unwrapped_bits[(idx*desired_width):(idx*desired_width+desired_width)])
+ rewrapped_array.append(ba2int(unwrapped_bits[(idx*desired_width):(idx*desired_width+desired_width)]))
+
+ return rewrapped_array
+
+def refolder(fake_array, *, fake_width, desired_width):
unwrapped_bits = bitarray("")
# unwrap the bits
@@ -63,7 +80,6 @@ def refolder(fake_array, fake_width, desired_width):
print("slicer", unwrapped_bits[(idx*desired_width):(idx*desired_width+desired_width)])
rewrapped_array.append(ba2int(unwrapped_bits[(idx*desired_width):(idx*desired_width+desired_width)]))
-
return rewrapped_array
@@ -126,7 +142,7 @@ class ArbitraryWidthMemory(Elaboratable):
m.submodules.read_port = read_port = self.backing_memory.read_port()
m.d.comb += read_port.addr.eq(fetch_address)
- m.d.comb += self.bus.r_data.eq(read_port.data)
+
shreg = Signal(self.fake_data_width)
current_slice = Signal(self.fake_data_width)
@@ -190,10 +206,10 @@ class ArbitraryWidthMemory(Elaboratable):
# So here we determine if there's any need for additional memory words:
m.d.comb += additional_words.eq(end_bit_pseudo_index[self.backing_memory_data_width_bits:])
- m.d.sync += shreg.eq(current_slice)
with m.If(additional_words == 0):
# No additional words, calculate which bits we need from the sole word we're fetching:
m.d.sync += MS_bit_index.eq(end_bit_pseudo_index[:self.backing_memory_data_width_bits])
+ m.d.comb += self.bus.r_data.eq(current_slice)
with m.Else():
# Additional words needed, so we fetch the entire remaining part of this word
@@ -206,7 +222,7 @@ class ArbitraryWidthMemory(Elaboratable):
m.d.sync += additional_words_regd.eq(additional_words)
m.d.sync += end_bit_pseudo_index_regd.eq(end_bit_pseudo_index)
- m.d.sync += shreg.eq(0)
+ m.d.sync += shreg.eq(current_slice)
m.next="MULTIPLE"
@@ -250,6 +266,9 @@ class ArbitraryWidthMemory(Elaboratable):
with m.If(lingering_txn == 1):
m.d.comb += bus.r_data.eq(last_r_data)
+ with m.If(bus.ready_in == 1):
+ m.next = "SINGLE"
+
return m
@@ -296,17 +315,55 @@ class DummyPlug(Elaboratable):
def elaborate(self, platform):
m = Module()
- m.submodules.FakeAWMem = FakeAWMem = ArbitraryWidthMemory(fake_data_width=16,
- fake_address_width=8, initial_data=[0xAB, 0xCD,0xEF,0x42], # refolder([10,9,8,7,6,5,4,3,2,1],4, 8),
+
+
+ fake_data_width=4
+ fake_address_width=8
+
+ backing_memory_data_width=8
+ backing_memory_address_width=8
+
+ fake_bits = fake_data_width * (2** fake_address_width)
+
+ real_bits = backing_memory_data_width * (2** backing_memory_address_width)
+
+ assert(fake_bits <= real_bits)
+
+ unwrapped_bits = urandom(fake_bits)
+ fake_array = folder(unwrapped_bits, desired_width=fake_data_width)
+
+ backing_array = folder(unwrapped_bits, desired_width=backing_memory_data_width)
+
+ m.submodules.AWMem = AWMem = ArbitraryWidthMemory(fake_data_width=4,
+ fake_address_width=8, initial_data=backing_array,
backing_memory_data_width=8, backing_memory_address_width=8)
- counter = Signal(8, reset=1)
- with m.If(FakeAWMem.bus.ready_out == 1):
- m.d.sync += counter.eq(counter+1)
+ m.submodules.FakeAWMem = FakeAWMem = GoldenArbitraryWidthMemory(data_width=fake_data_width, address_width=fake_address_width, sim_memory=fake_array)
+
+ for k in fake_array:
+ print(hex(k))
+ address = Signal(fake_address_width)
+ valid = Signal(1)
+ ready = Signal(1)
+
+ m.d.comb += FakeAWMem.bus.r_addr.eq(address)
+ m.d.comb += AWMem.bus.r_addr.eq(address)
+
+ m.d.comb += FakeAWMem.bus.valid_in.eq(valid)
+ m.d.comb += AWMem.bus.valid_in.eq(valid)
+
+ m.d.comb += FakeAWMem.bus.ready_in.eq(ready)
+ m.d.comb += AWMem.bus.ready_in.eq(ready)
+
+ counter = Signal(8, reset=0)
+ # with m.If(FakeAWMem.bus.ready_out == 1):
+ m.d.sync += counter.eq(counter+1)
+
+ with m.If(counter >= 8):
+ m.d.comb += ready.eq(1)
- #with m.If(counter == 4):
- m.d.comb += FakeAWMem.bus.valid_in.eq(1)
- m.d.comb += FakeAWMem.bus.r_addr.eq(counter)
+ m.d.comb += valid.eq(1)
+ m.d.comb += address.eq(counter)
return m
diff --git a/rtl_lib/arbitrary_width_memory.sby b/unoptimized_lr/rtl_lib/arbitrary_width_memory.sby
similarity index 100%
rename from rtl_lib/arbitrary_width_memory.sby
rename to unoptimized_lr/rtl_lib/arbitrary_width_memory.sby
diff --git a/rtl_lib/gearbox.py b/unoptimized_lr/rtl_lib/gearbox.py
similarity index 100%
rename from rtl_lib/gearbox.py
rename to unoptimized_lr/rtl_lib/gearbox.py
diff --git a/rtl_lib/gearbox.sby b/unoptimized_lr/rtl_lib/gearbox.sby
similarity index 100%
rename from rtl_lib/gearbox.sby
rename to unoptimized_lr/rtl_lib/gearbox.sby
diff --git a/rtl_lib/one_hot_utils.py b/unoptimized_lr/rtl_lib/one_hot_utils.py
similarity index 100%
rename from rtl_lib/one_hot_utils.py
rename to unoptimized_lr/rtl_lib/one_hot_utils.py
diff --git a/rtl_lib/pipe_stage.py b/unoptimized_lr/rtl_lib/pipe_stage.py
similarity index 100%
rename from rtl_lib/pipe_stage.py
rename to unoptimized_lr/rtl_lib/pipe_stage.py
diff --git a/rtl_lib/pipe_stage.sby b/unoptimized_lr/rtl_lib/pipe_stage.sby
similarity index 100%
rename from rtl_lib/pipe_stage.sby
rename to unoptimized_lr/rtl_lib/pipe_stage.sby
diff --git a/rtl_lib/shift_testing.py b/unoptimized_lr/rtl_lib/shift_testing.py
similarity index 100%
rename from rtl_lib/shift_testing.py
rename to unoptimized_lr/rtl_lib/shift_testing.py
diff --git a/rtl_lib/skidbuffer.py b/unoptimized_lr/rtl_lib/skidbuffer.py
similarity index 100%
rename from rtl_lib/skidbuffer.py
rename to unoptimized_lr/rtl_lib/skidbuffer.py
diff --git a/rtl_lib/width_converter_simulator.py b/unoptimized_lr/rtl_lib/width_converter_simulator.py
similarity index 100%
rename from rtl_lib/width_converter_simulator.py
rename to unoptimized_lr/rtl_lib/width_converter_simulator.py
diff --git a/unoptimized_lr/simple_lr_automaton.py b/unoptimized_lr/simple_lr_automaton.py
index 97b1c1b609768366751a0351dccc93457f9d467c..ff79e2ca0d8f656bfc14184f7d07eba1975b2c50 100644
--- a/unoptimized_lr/simple_lr_automaton.py
+++ b/unoptimized_lr/simple_lr_automaton.py
@@ -215,10 +215,11 @@ class ParametrizationConstants():
class SimpleLRAutomaton(Elaboratable):
- def __init__(self):
+ def __init__(self, *, lr_tables, parameters):
# Stack
self.mem = Memory(width=self.table_width, depth=self.table_depth, init=rasterized)
-
+ self.lr_tables = lr_tables
+ self.parameters = parameters
def elaborate(self, platform):
m = Module()