diff --git a/combinatorial_LR_parser.py b/combinatorial_LR_parser.py index bf90631d543725a82cbff86a19b5e8d406a99851..8decdca9a8162787e2b0222e766eea34fc451e88 100644 --- a/combinatorial_LR_parser.py +++ b/combinatorial_LR_parser.py @@ -579,7 +579,8 @@ class TreeSerializer(Elaboratable): # incremented each cycle number_written = Signal(range(self.stack_depth)) - + m.d.comb += self.serialized_index.eq(start_of_record) + with m.FSM() as fsm: @@ -603,7 +604,10 @@ class TreeSerializer(Elaboratable): m.d.sync += item_created_by_reduce_rule.eq(self.item_created_by_reduce_rule) with m.If(self.start_reduction == 1): - m.d.comb += self.memory_write_port.eq(self.destroyed_item_in) + with m.If(self.destroyed_item_index_in == 0): + m.d.comb += self.memory_write_port.eq(self.destroyed_item_in) + with m.Else(): + m.d.comb += self.memory_write_port.eq(self.destroyed_item_index_in) m.d.comb += self.memory_address_port.eq(start_of_record + 2) m.d.comb += self.memory_write_enable.eq(1) @@ -615,7 +619,10 @@ class TreeSerializer(Elaboratable): with m.State("SUBNODES"): m.d.comb += self.ready_out.eq(0) with m.If(self.destroyed_item_valid_in == 1): - m.d.comb += self.memory_write_port.eq(self.destroyed_item_in) + with m.If(self.destroyed_item_index_in == 0): + m.d.comb += self.memory_write_port.eq(self.destroyed_item_in) + with m.Else(): + m.d.comb += self.memory_write_port.eq(self.destroyed_item_index_in) m.d.comb += self.memory_address_port.eq(start_of_record + 2 + number_written) m.d.comb += self.memory_write_enable.eq(1) @@ -747,7 +754,7 @@ class MasterStateMachine(Elaboratable): m.d.comb += fsm_ready.eq(0) m.d.comb += doublestacks.command_in_strobe.eq(1) m.d.comb += doublestacks.big_push_port.eq(0x5a00) - m.d.comb += doublestacks.side_push_port.eq(0x80) + m.d.comb += doublestacks.side_push_port.eq(0x00) m.d.comb += doublestacks.command_in.eq(2) @@ -767,7 +774,7 @@ class MasterStateMachine(Elaboratable): m.d.comb += doublestacks.command_in.eq(2) m.d.comb += doublestacks.command_in_strobe.eq(1) m.d.comb += doublestacks.big_push_port.eq(new_item) - m.d.comb += doublestacks.side_push_port.eq(0x80) + m.d.comb += doublestacks.side_push_port.eq(0x00) m.d.comb += fsm_ready.eq(1) with m.If((rule_matcher.force_shift == 0) & (rule_matcher.match_index_out == 0)): @@ -829,7 +836,7 @@ class MasterStateMachine(Elaboratable): with m.If(number_to_pop == 0): m.d.comb += doublestacks.command_in.eq(2) m.d.comb += doublestacks.big_push_port.eq(execution_result) - m.d.comb += doublestacks.side_push_port.eq(0xf0) + m.d.comb += doublestacks.side_push_port.eq(serializer.serialized_index) m.d.comb += doublestacks.command_in_strobe.eq(1) # m.d.comb += fsm_ready.eq(1) @@ -876,7 +883,7 @@ class DummyPlug(Elaboratable): m = Module() # BOTTOM = start of parse - mem = Memory(width=16, depth=256, init=[OPENPAREN, OPENPAREN, 0XE102, CLOSEPAREN, ADDOP, 0xE107, CLOSEPAREN, ENDOFPARSE]) + mem = Memory(width=16, depth=256, init=[0XE102, ENDOFPARSE]) m.submodules.parse_data = rdport = mem.read_port()