diff --git a/gearbox.py b/gearbox.py
index 57b227146c1411591c012b7edc78511732390fcd..1ffb0f4c685dbd44faf8c0a080d44725727f36a3 100755
--- a/gearbox.py
+++ b/gearbox.py
@@ -4,6 +4,13 @@ from nmigen.hdl.rec import *
 from nmigen.cli import main
 
 
+# NEXT TASKS (IMMEDIATE)
+# finish fleshing out code, attach buses from the Flow controller to the gearbox
+# do the write-logic
+# figure out how the Altera gearbox design works (number of pipeline stages and what each does)
+
+
+
 
 # REMAINING WORK
 #
@@ -12,6 +19,11 @@ from nmigen.cli import main
 # as that coming in (can do with PRBS) and that bus interface constraints are not violated
 
 
+# can make a testbench only operating on the indices and the flowcontrol signals that keeps a
+# model of the valid/invalid bits and verifies that when a transaction happens, the right bits
+# get read/written and the right indices get moved in the right ways
+
+
 class IndexDisambiguator(Enum):
     LAST_OP_UNKNOWN = 0
     LAST_OP_WAS_WRITE = 1