From d5a4e92305a0e2e8d4bbb8f9560c123623318ffa Mon Sep 17 00:00:00 2001
From: Kia <kia@special-circumstanc.es>
Date: Mon, 25 Jan 2021 19:43:31 -0700
Subject: [PATCH] GOTO table with the bus instead of individual signals
---
unoptimized_lr/simple_lr_table.py | 58 +++++++++++++------------------
1 file changed, 24 insertions(+), 34 deletions(-)
diff --git a/unoptimized_lr/simple_lr_table.py b/unoptimized_lr/simple_lr_table.py
index df6e316..3bf7947 100644
--- a/unoptimized_lr/simple_lr_table.py
+++ b/unoptimized_lr/simple_lr_table.py
@@ -21,12 +21,12 @@ from functools import reduce
class TableBusLayout(Layout):
def __init__(self, *, row_input_width, column_input_width, output_width):
super().__init__([
- ("row_idx", unsigned(row_input_width)),
- ("col_idx", unsigned(column_input_width)),
+ ("row_idx", unsigned(row_input_width)),
+ ("col_idx", unsigned(column_input_width)),
("output_data", unsigned(output_width)),
- ("valid_in", 1),
- ("valid_out", 1),
- ("ready_out", 1),
+ ("valid_in", 1),
+ ("valid_out", 1),
+ ("ready_out", 1),
])
class TableBus(Record):
@@ -68,7 +68,6 @@ class LRTable(Elaboratable):
# Interfaces
-
# Input data:
self.state_in = Signal(range(number_of_states))
self.terminal_in = Signal(range(number_of_terminals))
@@ -162,22 +161,14 @@ class GOTOtable(Elaboratable):
self.number_of_nonterminals = number_of_nonterminals
- # Interfaces
-
- # Input data:
- self.state_in = Signal(range(number_of_states))
- self.nonterminal_in = Signal(range(number_of_nonterminals))
- # Control
- self.in_valid = Signal(1)
-
- # Output data:
+ dummy_row = Signal(range(number_of_states))
+ dummy_column = Signal(range(number_of_nonterminals))
- self.table_entry_out = Signal(self.table_width)
-
-
- # Output control
- self.table_entry_out_valid = Signal(1)
+ # Interfaces
+ self.bus = TableBus(row_input_width=len(dummy_row),
+ column_input_width=len(dummy_column),
+ output_width=self.table_width)
# Prepare the table for consumption
@@ -189,7 +180,6 @@ class GOTOtable(Elaboratable):
rasterized.extend(row)
# Memory
- self.bus = TableBus(row_input_width=4, column_input_width=5, output_width=42)
self.mem = Memory(width=self.table_width, depth=self.table_depth, init=rasterized)
@@ -200,14 +190,14 @@ class GOTOtable(Elaboratable):
m.submodules.wport = wport = (self.mem).write_port()
- m.d.sync += self.table_entry_out_valid.eq(self.in_valid)
+ m.d.sync += self.bus.valid_out.eq(self.bus.valid_in)
# Now we calculate the address:
tgt_address = Signal(self.table_depth)
- m.d.comb += tgt_address.eq(self.state_in * self.number_of_nonterminals + self.nonterminal_in)
+ m.d.comb += tgt_address.eq(self.bus.row_idx * self.number_of_nonterminals + self.bus.col_idx)
m.d.comb += rport.addr.eq(tgt_address)
- m.d.comb += self.table_entry_out.eq((rport.data))
+ m.d.comb += self.bus.output_data.eq((rport.data))
@@ -225,22 +215,22 @@ class DummyPlug(Elaboratable):
def elaborate(self, platform):
m = Module()
- m.submodules.table = table = GOTOtable(3,3,[[1,2,3],[4,5,6],[7,0,1]])
+ m.submodules.table = table = GOTOtable(3,3,[[1,2,3],[4,5,6],[1,7,1]])
counter = Signal(8)
m.d.sync += counter.eq(counter+1)
with m.If(counter == 3):
- m.d.comb += table.in_valid.eq(1)
- m.d.comb += table.state_in.eq(0)
- m.d.comb += table.nonterminal_in.eq(0)
+ m.d.comb += table.bus.valid_in.eq(1)
+ m.d.comb += table.bus.row_idx.eq(0)
+ m.d.comb += table.bus.col_idx.eq(0)
with m.If(counter == 4):
- m.d.comb += table.in_valid.eq(1)
- m.d.comb += table.state_in.eq(0)
- m.d.comb += table.nonterminal_in.eq(1)
+ m.d.comb += table.bus.valid_in.eq(1)
+ m.d.comb += table.bus.row_idx.eq(0)
+ m.d.comb += table.bus.col_idx.eq(1)
with m.If(counter == 6):
- m.d.comb += table.in_valid.eq(1)
- m.d.comb += table.state_in.eq(2)
- m.d.comb += table.nonterminal_in.eq(0)
+ m.d.comb += table.bus.valid_in.eq(1)
+ m.d.comb += table.bus.row_idx.eq(2)
+ m.d.comb += table.bus.col_idx.eq(1)
return m
--
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