From d84f0294105a267590da205633fd03ee9e131c80 Mon Sep 17 00:00:00 2001
From: Kia <kia@special-circumstanc.es>
Date: Wed, 14 Apr 2021 13:52:33 -0600
Subject: [PATCH] we've decided to accept the extra clock cycle from now
---
rtl_lib/arbitrary_width_memory.py | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/rtl_lib/arbitrary_width_memory.py b/rtl_lib/arbitrary_width_memory.py
index 464a923..680fef1 100644
--- a/rtl_lib/arbitrary_width_memory.py
+++ b/rtl_lib/arbitrary_width_memory.py
@@ -36,9 +36,6 @@ class ArbitraryWidthMemoryBus(Record):
super().__init__(ArbitraryWidthMemoryLayout(data_width=data_width, address_width=address_width))
-# initial_data must be folded, spindled, and mutilated to fit inside the backing memory dimensions
-
-# later on we will write a function to take care of this automatically
def refolder(fake_array, fake_width, desired_width):
@@ -160,7 +157,7 @@ class ArbitraryWidthMemory(Elaboratable):
with m.FSM() as fsm:
with m.State("RESET"):
- m.next ="READY"
+ m.next ="SINGLE"
with m.State("SINGLE"):
m.d.comb += bus.ready_out.eq(1)
@@ -209,7 +206,7 @@ class ArbitraryWidthMemory(Elaboratable):
m.d.sync += additional_words_regd.eq(additional_words)
m.d.sync += end_bit_pseudo_index_regd.eq(end_bit_pseudo_index)
- m.d.sync += shreg.eq(shreg << (shreg_new_bits) | current_slice)
+ m.d.sync += shreg.eq(0)
m.next="MULTIPLE"
@@ -244,13 +241,14 @@ class ArbitraryWidthMemory(Elaboratable):
with m.State("FINALIZE"):
# final word fetch has happened, we now slice it and present it on the downstream data interface
+ m.d.comb += bus.valid_out.eq(1)
+
with m.If(lingering_txn == 0):
m.d.comb += bus.r_data.eq( shreg << (shreg_new_bits) | current_slice)
m.d.sync += last_r_data.eq(shreg << (shreg_new_bits) | current_slice)
m.d.sync += lingering_txn.eq(1)
with m.If(lingering_txn == 1):
m.d.comb += bus.r_data.eq(last_r_data)
- m.d.comb += bus.valid_out.eq(1)
return m
@@ -299,9 +297,9 @@ class DummyPlug(Elaboratable):
m = Module()
m.submodules.FakeAWMem = FakeAWMem = ArbitraryWidthMemory(fake_data_width=16,
- fake_address_width=8, initial_data=[0xBA, 0xDC,0xFE], # refolder([10,9,8,7,6,5,4,3,2,1],4, 8),
+ fake_address_width=8, initial_data=[0xAB, 0xCD,0xEF,0x42], # refolder([10,9,8,7,6,5,4,3,2,1],4, 8),
backing_memory_data_width=8, backing_memory_address_width=8)
- counter = Signal(8, reset=0)
+ counter = Signal(8, reset=1)
with m.If(FakeAWMem.bus.ready_out == 1):
m.d.sync += counter.eq(counter+1)
--
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