From e359781a69dda943985c1aafededfa7b86517491 Mon Sep 17 00:00:00 2001
From: Kia <kia@special-circumstanc.es>
Date: Thu, 14 Jan 2021 19:02:38 -0700
Subject: [PATCH] seems to work
---
unoptimized_lr/simple_lr_table.py | 30 ++++++++++++++++++++++--------
1 file changed, 22 insertions(+), 8 deletions(-)
diff --git a/unoptimized_lr/simple_lr_table.py b/unoptimized_lr/simple_lr_table.py
index af56af6..78b2857 100644
--- a/unoptimized_lr/simple_lr_table.py
+++ b/unoptimized_lr/simple_lr_table.py
@@ -9,7 +9,10 @@ from functools import reduce
# we can get a gold-standard/reference implementation, against which we can test
# our further optimizations, including compression and non-standard representations.
-
+# TODO PLAN:
+# 1) get this working in simulation
+# 2) make it synthesizable (so it can use FPGA block RAM with reasonable bit-width)
+# 3) make it optimized
class LRTable(Elaboratable):
def __init__(self, number_of_states, number_of_terminals, number_of_reduce_rules):
@@ -40,8 +43,8 @@ class LRTable(Elaboratable):
reduce_rule_signal = Signal(range(number_of_reduce_rules))
reduce_rule_bits = len(reduce_rule_signal)
- table_entry_width = (reduce_rule_bits + 2)
- self.table_width = number_of_terminals * table_entry_width
+ self.table_entry_width = (reduce_rule_bits + 2)
+ self.table_width = number_of_terminals * self.table_entry_width
self.table_depth = number_of_states
@@ -56,7 +59,7 @@ class LRTable(Elaboratable):
# Output data:
- self.table_entry_out = Signal(table_entry_width)
+ self.table_entry_out = Signal(self.table_entry_width)
# Output control
@@ -64,7 +67,7 @@ class LRTable(Elaboratable):
# Memory
- self.mem = Memory(width=self.table_width, depth=self.table_depth, init= [4,5,6,7])
+ self.mem = Memory(width=self.table_width, depth=self.table_depth, init= [0x1a,0x2b,0x3c,0x4d])
def elaborate(self, platform):
@@ -75,11 +78,18 @@ class LRTable(Elaboratable):
m.d.comb += row_address.eq(self.state_in)
m.d.comb += rport.addr.eq(row_address)
- m.d.comb += self.table_entry_out.eq(rport.data)
m.d.sync += self.table_entry_out_valid.eq(self.in_valid)
+ # Now we calculate the column address:
+
+ registered_column = Signal(len(self.terminal_in))
+
+ m.d.sync += registered_column.eq(self.terminal_in)
+
+
+ m.d.comb += self.table_entry_out.eq((rport.data).word_select(registered_column, self.table_entry_width))
@@ -101,11 +111,15 @@ class DummyPlug(Elaboratable):
with m.If(counter == 3):
m.d.comb += table.in_valid.eq(1)
- m.d.comb += table.state_in.eq(2)
+ m.d.comb += table.state_in.eq(1)
+ m.d.comb += table.terminal_in.eq(0)
with m.If(counter == 4):
+ m.d.comb += table.in_valid.eq(1)
+ m.d.comb += table.state_in.eq(2)
+ with m.If(counter == 6):
m.d.comb += table.in_valid.eq(1)
m.d.comb += table.state_in.eq(3)
-
+ m.d.comb += table.terminal_in.eq(0)
return m
--
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