From ece3d518d452b69f3aeb48ad311d8b528cf17a6f Mon Sep 17 00:00:00 2001
From: Kia <kia@special-circumstanc.es>
Date: Sun, 4 Apr 2021 20:32:50 -0600
Subject: [PATCH] rm now-superfluous comments
---
rtl_lib/arbitrary_width_memory.py | 16 ----------------
1 file changed, 16 deletions(-)
diff --git a/rtl_lib/arbitrary_width_memory.py b/rtl_lib/arbitrary_width_memory.py
index f249ce7..dad9860 100644
--- a/rtl_lib/arbitrary_width_memory.py
+++ b/rtl_lib/arbitrary_width_memory.py
@@ -98,13 +98,6 @@ class ArbitraryWidthMemory(Elaboratable):
m.d.comb += read_port.addr.eq(fetch_address)
m.d.comb += self.bus.r_data.eq(read_port.data)
-
-
-
- # combining shift reg
-
- # the register itself
-
shreg = Signal(self.fake_data_width)
current_slice = Signal(self.backing_memory_data_width)
lower_bits_cut = Signal(self.backing_memory_data_width)
@@ -123,15 +116,6 @@ class ArbitraryWidthMemory(Elaboratable):
m.d.comb += shreg_new_bits.eq(MS_bit_index-LS_bit_index+1)
-# is like a gear box but with variable upstream elnght
-
-# thats it
-
-# we should do this)
-
-
-
-
with m.FSM() as fsm:
with m.State("RESET"):
--
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