diff --git a/rtl_lib/arbitrary_width_memory.py b/rtl_lib/arbitrary_width_memory.py
index 5b386823a1bde1c098ecf0b9783a465896d7f9ae..16bf2a3806e1a05820e30821b55709e98b6c1d98 100644
--- a/rtl_lib/arbitrary_width_memory.py
+++ b/rtl_lib/arbitrary_width_memory.py
@@ -118,7 +118,10 @@ class ArbitraryWidthMemory(Elaboratable):
 
             m.d.comb += lower_bits_cut.eq(read_port.data>>LS_bit_index)
 
-            m.d.comb += current_slice.eq(((lower_bits_cut<<MS_bit_index)&0xff)>>MS_bit_index)
+            top_cut = Signal(range(self.backing_memory_data_width+1))
+
+            m.d.comb += top_cut.eq(self.backing_memory_data_width-MS_bit_index-1)
+            m.d.comb += current_slice.eq(((lower_bits_cut<<top_cut)&0xff)>>top_cut)
 
             m.d.comb += shreg_new_bits.eq(MS_bit_index-LS_bit_index+1)
 
@@ -252,7 +255,7 @@ class DummyPlug(Elaboratable):
         m = Module()
 
         m.submodules.FakeAWMem = FakeAWMem = ArbitraryWidthMemory(fake_data_width=7,
-                            fake_address_width=8, initial_data=[0x23,0x45, 0x67, 0x89, 0xab,0xcd,0xef],
+                            fake_address_width=8, initial_data=[0xff,0xff, 0xff, 0xff, 0xff,0xff,0xff,],
                             backing_memory_data_width=8, backing_memory_address_width=8)
         counter = Signal(8, reset=1)