From f6456b0c57ff9b8040e838fe185dce4b067ec85f Mon Sep 17 00:00:00 2001
From: Kia <kia@special-circumstanc.es>
Date: Tue, 2 Feb 2021 15:36:19 -0700
Subject: [PATCH] getting closer
---
gearbox.py | 98 ++++++++++++++++++++++++++++++++++++------------------
1 file changed, 65 insertions(+), 33 deletions(-)
diff --git a/gearbox.py b/gearbox.py
index 8f03f8a..a48036c 100755
--- a/gearbox.py
+++ b/gearbox.py
@@ -1,23 +1,66 @@
from nmigen import *
+from nmigen.hdl.rec import *
+
from nmigen.cli import main
-class ArbitraryGearbox(Elaboratable): # non-registered
- def __init__(self, i_width, o_width):
- self.i_width = i_width
- self.o_width = o_width
+class GearboxBusLayout(Layout):
+ def __init__(self, *, in_width, out_width):
+ super().__init__([
+ # DATA
+ ("data_in", unsigned(in_width)), # FROM SOURCE
+ ("data_out", unsigned(out_width)), # TO DEST
+
+ # CONTROL
+ ("valid_in", 1), # FROM SOURCE
+ ("ready_out", 1), # TO SOURCE
+
+ ("ready_in", 1), # FROM DEST
+ ("valid_out", 1), # TO DEST
+
+ ])
+
+class GearboxBus(Record):
+ def __init__(self, *, in_width, out_width):
+ super().__init__(GearboxBusLayout(in_width=in_width, out_width=out_width))
+
+class ArbitraryGearbox(Elaboratable):
+ def __init__(self, *, in_width, out_width):
+ self.in_width = in_width
+ self.out_width = out_width
- self.upstream_data_in = Signal(self.i_width)
- self.downstream_data_out = Signal(self.o_width)
+ self.bus = GearboxBus(in_width=in_width, out_width=out_width)
def elaborate(self, platform):
m = Module()
+ loop = Signal(1)
+ len_storage = self.in_width + self.out_width
+ #storage = Signal(len_storage, reset=0b001_010_011_100_101_110_111)
+ #storage = Signal(len_storage, reset= 0b111_110_101_100_011_010_001)
+
+
+ storage = Signal(len_storage, reset= 0b100_000_000_000_000_000_000)
- len_storage = self.i_width + self.o_width
- storage = Signal(len_storage)
write_ptr = Signal(range(len_storage))
- read_ptr = Signal(range(len_storage))
+ read_ptr = Signal(range(len_storage), reset=2)
+
+ # read index logic here
+ with m.If(read_ptr + self.out_width >= len_storage):
+ m.d.sync += read_ptr.eq(read_ptr + self.out_width - len_storage)
+ m.d.comb += loop.eq(1)
+ with m.Else():
+ m.d.sync += read_ptr.eq(read_ptr + self.out_width)
+
+ # read-out case analysis here:
+
+ with m.If(read_ptr + self.out_width <= len_storage):
+ m.d.comb += self.bus.data_out.eq(storage.bit_select(read_ptr, self.out_width))
+ with m.Else():
+ m.d.comb += self.bus.data_out.eq(storage.bit_select(read_ptr, len_storage - self.out_width))
+
+
+
return m
@@ -25,38 +68,27 @@ class ArbitraryGearbox(Elaboratable): # non-registered
class DummyPlug(Elaboratable):
- def elaborate(self, platform):
- m = Module()
- egg = RegisteredSkidBuffer(8)
- m.submodules += egg
- cntr = Signal(8)
- intctr = Signal(8)
- data_in = Signal(8)
- m.d.sync += intctr.eq(intctr +1)
- m.d.comb += egg.upstream_data_in.eq(data_in)
+ #def __init__(self):
- upstream_valid = Signal(1)
- m.d.comb += egg.upstream_valid_in.eq(upstream_valid)
- m.d.comb += upstream_valid.eq(1)
- downstream_ready = Signal(1)
- m.d.comb += egg.downstream_ready_in.eq(downstream_ready)
- m.d.comb += downstream_ready.eq(1)
- m.d.comb += data_in.eq(cntr)
- with m.If((intctr == 4) | (intctr == 5) | (intctr == 6)):
- m.d.comb += downstream_ready.eq(0)
-# with m.If((intctr == 4) | (intctr == 5)):
-# m.d.comb += upstream_valid.eq(0)
-# m.d.comb += data_in.eq(0)
- with m.If(egg.upstream_ready_out == 1):
- m.d.sync += cntr.eq(cntr+1)
+ def elaborate(self, platform):
+ m = Module()
+
+ m.submodules.table = table = ArbitraryGearbox(in_width=(21-3), out_width=3)
+ counter = Signal(8)
+ m.d.sync += counter.eq(counter+1)
+
+ with m.If(counter == 3):
+ m.d.comb += table.bus.data_in.eq(1)
return m
+
if __name__ == '__main__':
baka =DummyPlug()
- main(baka)
\ No newline at end of file
+ main(baka)
+ #platform.build(DummyPlug())
--
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