From fe5ba519a78ae92ac09b8692a251fdbde320cfd6 Mon Sep 17 00:00:00 2001
From: Kia <kia@special-circumstanc.es>
Date: Mon, 24 Aug 2020 17:16:48 -0600
Subject: [PATCH] reorder
---
python_arborist.py | 90 +++++++++++++++++++++++-----------------------
1 file changed, 44 insertions(+), 46 deletions(-)
diff --git a/python_arborist.py b/python_arborist.py
index 7c37aa3..79e4ac1 100644
--- a/python_arborist.py
+++ b/python_arborist.py
@@ -265,6 +265,48 @@ class Cirno(Elaboratable):
return m
+def run_the_sim():
+ m = Module()
+ m.submodules.baka = nine = Cirno()
+
+ def process():
+ while True:
+ z = yield nine.finalized
+# print(z)
+ if(z==0):
+ yield
+ z = yield nine.finalized
+# print(z)
+
+ array = []
+ for idx in range(128):
+ #print(idx)
+ x = yield nine.tapir[idx]
+ array.append(x)
+ trace.append(array)
+ else:
+ break
+
+
+
+ with m.Switch(nine.input_memory_addr):
+ for addr,data in enumerate(parse_me):
+ with m.Case(addr):
+ #print(addr,data)
+ m.d.sync += nine.input_memory_data.eq(data)
+ with m.Default():
+ m.d.sync += nine.input_memory_data.eq(0xf00d)
+
+
+ sim = Simulator(m)
+ sim.add_clock(1e-9)
+ sim.add_sync_process(process)
+ with sim.write_vcd("test.vcd", "test.gtkw"):
+ sim.run()
+
+ for x in trace:
+ print(x)
+
tokens ={
"BOTTOM": 0x5a00,
@@ -324,54 +366,10 @@ parse_me = bgen[0]
parse_me.append(ENDOFPARSE)
+trace = []
-
-
-
-if __name__ == '__main__':
- m = Module()
- m.submodules.baka = nine = Cirno()
-
- trace = []
- def process():
- while True:
- z = yield nine.finalized
-# print(z)
- if(z==0):
- yield
- z = yield nine.finalized
-# print(z)
-
- array = []
- for idx in range(128):
- #print(idx)
- x = yield nine.tapir[idx]
- array.append(x)
- trace.append(array)
- else:
- break
-
-
-
- with m.Switch(nine.input_memory_addr):
- for addr,data in enumerate(parse_me):
- with m.Case(addr):
- #print(addr,data)
- m.d.sync += nine.input_memory_data.eq(data)
- with m.Default():
- m.d.sync += nine.input_memory_data.eq(0xf00d)
-
-
- sim = Simulator(m)
- sim.add_clock(1e-9)
- sim.add_sync_process(process)
- with sim.write_vcd("test.vcd", "test.gtkw"):
- sim.run()
-
- for x in trace:
- print(x)
-
+run_the_sim()
serialized_tree_final = trace[-1]
print()
--
GitLab