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from nmigen import *
from nmigen.cli import main
class ArbitraryGearbox(Elaboratable): # non-registered
def __init__(self, i_width, o_width):
self.i_width = i_width
self.o_width = o_width
self.upstream_data_in = Signal(self.i_width)
self.downstream_data_out = Signal(self.o_width)
def elaborate(self, platform):
m = Module()
len_storage = self.i_width + self.o_width
storage = Signal(len_storage)
write_ptr = Signal(range(len_storage))
read_ptr = Signal(range(len_storage))
return m
class DummyPlug(Elaboratable):
def elaborate(self, platform):
m = Module()
egg = RegisteredSkidBuffer(8)
m.submodules += egg
cntr = Signal(8)
intctr = Signal(8)
data_in = Signal(8)
m.d.sync += intctr.eq(intctr +1)
m.d.comb += egg.upstream_data_in.eq(data_in)
upstream_valid = Signal(1)
m.d.comb += egg.upstream_valid_in.eq(upstream_valid)
m.d.comb += upstream_valid.eq(1)
downstream_ready = Signal(1)
m.d.comb += egg.downstream_ready_in.eq(downstream_ready)
m.d.comb += downstream_ready.eq(1)
m.d.comb += data_in.eq(cntr)
with m.If((intctr == 4) | (intctr == 5) | (intctr == 6)):
m.d.comb += downstream_ready.eq(0)
# with m.If((intctr == 4) | (intctr == 5)):
# m.d.comb += upstream_valid.eq(0)
# m.d.comb += data_in.eq(0)
with m.If(egg.upstream_ready_out == 1):
m.d.sync += cntr.eq(cntr+1)
return m
if __name__ == '__main__':
baka =DummyPlug()
main(baka)