This code is an implementation of an LR(1) parser written in nMigen, a python-based hardware description language. This means that it is possible to use the synthesized output as an IP core/block in an FPGA design. At compile/synthesis time, you will provide the software with parametrization information that includes:
This code is an implementation of an LR(1) parser written in nMigen, a python-based hardware description language. This means that it is possible to use the synthesized output as an IP core/block in an FPGA design.
## Parametrization Interface
At compile/synthesis time, you will provide the software with parametrization information that includes:
* The complete language specification
* The complete language specification
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* at the nMigen level. nMigen has an integrated simulator, which is less performant than either Verilator or cxxrtl, but allows for easy integration with the nMigen code.
* at the nMigen level. nMigen has an integrated simulator, which is less performant than either Verilator or cxxrtl, but allows for easy integration with the nMigen code.
## HDL/Gateware Interface
The synthesized design expresses two data interfaces, the input and output, and several sideband signals. The input data port has a "ready" output, and a "valid" input, which allow for flow control when interfacing with upstream components, and the output data port has a "valid" output and a "ready" input, which allow for flow control when interfacing with downstream components. Currently, the output data port is connected to a RAM, for ease in simulation/testing, but this is arbitrary and will be removed.
The synthesized design expresses two data interfaces, the input and output, and several sideband signals. The input data port has a "ready" output, and a "valid" input, which allow for flow control when interfacing with upstream components, and the output data port has a "valid" output and a "ready" input, which allow for flow control when interfacing with downstream components. Currently, the output data port is connected to a RAM, for ease in simulation/testing, but this is arbitrary and will be removed.
The sideband signals do not carry the bulk of the data, but are critical to proper operation of the parser and correct use of its results. The sideband signals are:
The sideband signals do not carry the bulk of the data, but are critical to proper operation of the parser and correct use of its results. The sideband signals are:
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@@ -38,12 +46,16 @@ The sideband signals do not carry the bulk of the data, but are critical to prop
## Design
## Design
## Parametrization Interface
## HDL/Gateware Interface
## Work left to do
## Work left to do
## Installation instructions and dependencies
## Installation instructions and dependencies
A recent version of Python 3 is required, as is nMigen, which can be installed with:
