try working on combining shift register, we morally are on the right track but...

try working on combining shift register, we morally are on the right track but need to finetune the indexing and make sure the boundary cases don't break stuff)

rtl_lib/arbitrary_width_memory.py

@@ -5,6 +5,11 @@ from nmigen.asserts import *
 from nmigen.cli import main
 
 
+# WARNING!
+# Signal(range(8)) will generate a THREE(3) wide signal, not enough to store 8
+# we need to check all our widths to verify we haven't fallen prey to this
+
+# we need to harmonize the terminology of "left" and "right" with LSB and MSB type terminology
 
 
 class ArbitraryWidthMemoryLayout(Layout):
@@ -95,6 +100,38 @@ class ArbitraryWidthMemory(Elaboratable):
             m.d.comb += read_port.addr.eq(fetch_address)
             m.d.comb += self.bus.r_data.eq(read_port.data)
 
+
+
+
+            # combining shift reg
+
+            # the register itself
+
+            shreg = Signal(self.fake_data_width)
+            current_slice = Signal(self.backing_memory_data_width)
+            lower_bits_cut = Signal(self.backing_memory_data_width)
+
+            valid_shreg_bits = Signal(range(self.fake_data_width))
+            shreg_new_bits = Signal(range(self.backing_memory_data_width+1))
+
+            m.d.sync += shreg.eq(shreg << (shreg_new_bits) | current_slice)
+
+            m.d.comb += lower_bits_cut.eq(read_port.data>>left_bit_index)
+
+            m.d.comb += current_slice.eq(((lower_bits_cut<<right_bit_index)&0xff)>>right_bit_index)
+
+            m.d.comb += shreg_new_bits.eq(right_bit_index-left_bit_index+1)
+
+#                is like a gear box but with variable upstream elnght
+
+#                thats it
+
+#                we should do this)
+
+
+
+
+
             with m.FSM() as fsm:
                 with m.State("RESET"):
                     m.next ="READY"
@@ -214,7 +251,7 @@ class DummyPlug(Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
-        m.submodules.FakeAWMem = FakeAWMem = ArbitraryWidthMemory(fake_data_width=9,
+        m.submodules.FakeAWMem = FakeAWMem = ArbitraryWidthMemory(fake_data_width=7,
                             fake_address_width=8, initial_data=[0x23,0x45, 0x67, 0x89, 0xab,0xcd,0xef],
                             backing_memory_data_width=8, backing_memory_address_width=8)
         counter = Signal(8, reset=1)