readout logic seems to work :)

gearbox.py

@@ -40,7 +40,7 @@ class ArbitraryGearbox(Elaboratable):
             #storage   = Signal(len_storage, reset= 0b111_110_101_100_011_010_001)
 
 
-            storage   = Signal(len_storage, reset= 0b100_000_000_000_000_000_000)
+            storage   = Signal(len_storage, reset= 0b1_100_011_00)
 
             write_ptr = Signal(range(len_storage))
             read_ptr  = Signal(range(len_storage), reset=2)
@@ -48,7 +48,6 @@ class ArbitraryGearbox(Elaboratable):
             # read index logic here
             with m.If(read_ptr + self.out_width >= len_storage):
                 m.d.sync += read_ptr.eq(read_ptr + self.out_width - len_storage)
-                m.d.comb += loop.eq(1)
             with m.Else():
                 m.d.sync += read_ptr.eq(read_ptr + self.out_width)
 
@@ -57,7 +56,16 @@ class ArbitraryGearbox(Elaboratable):
             with m.If(read_ptr + self.out_width <= len_storage):
                 m.d.comb += self.bus.data_out.eq(storage.bit_select(read_ptr, self.out_width))
             with m.Else():
-                m.d.comb += self.bus.data_out.eq(storage.bit_select(read_ptr, len_storage - self.out_width))
+                with m.Switch(read_ptr):
+                    for cand_rptr in range(len_storage - self.out_width + 1, len_storage):
+                        with m.Case(cand_rptr):
+                            m.d.comb += loop.eq(1)
+                            non_wrapping_bitwidth = len_storage - cand_rptr
+                            wrapping_bitwidth     = self.out_width + cand_rptr - len_storage
+                            m.d.comb += self.bus.data_out.eq(Cat(
+                                storage.bit_select(cand_rptr, non_wrapping_bitwidth), # the non-wrapping bits are less-significant
+                                storage.bit_select(0,         wrapping_bitwidth)      # ...than the wrapping bit
+                                ))
 
 
 
@@ -76,7 +84,7 @@ class DummyPlug(Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
-        m.submodules.table = table = ArbitraryGearbox(in_width=(21-3), out_width=3)
+        m.submodules.table = table = ArbitraryGearbox(in_width=(9-3), out_width=3)
         counter = Signal(8)
         m.d.sync += counter.eq(counter+1)