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Hammer FPGA backend
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Kia
Hammer FPGA backend
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da549843ce4a75fa736a33028788042c76bb538f
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Created with Raphaël 2.2.0
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CFG now
master
master
this is actually the hard-mode CFG (technically it's also a regular language but whatever that's fine!)
use the all-inclusive external bus definition instead
qualify variables
update naming after previous renames
add code to create the records
move buses/layouts into single file
write more subcomponent bus interface definitions
add calculation for width of serialization bus/memory
add index stack interface
explain width of parse tree stream
add parse stack interface
terminology rename; "StackItems" is confusing because it's unclear whether it refers to the width of the item or the width of the index needed to address them. We select "StackDepth" because that's a bit more clear, hopefully.
remove command_width as parameter
add underscores, restate data_out widths for the stacks
start including the subcomponent's layouts inside the top-level internal bus layout
reduce table renames
stack renames
likewise for the GOTO table's bus Layout
rename
shift/reduce table Layout done the right way
fixed typo
repeat ourselves a bit
spacing
redoing the table/stack Layouts to just take the language parameters; also fixed bug where we were mistakenly indexing by nonterminals and not reduce rules
reorder
spacing
conditionally add the components necessary for serializing if we're asked to generate a parse tree
split Layouts into internals/externals
reorder two tables in the documentation
module
imports
move directory to facilitate importing
we've decided to accept the extra clock cycle from now
start typing up notes on research directions and more advanced microarchitectures
start working on downstream transaction flow control (the case where we present data but downstream isn't ready yet)
document slicer
attempt to fix the desync bug
test using the internal nMigen "Part" function from nmigen.hdl.ast to see if we can do variable-width slicing but no alas it fails
restore omitted line, use the refolder to initialize the memory
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