rm now-superfluous comments

rtl_lib/arbitrary_width_memory.py

@@ -98,13 +98,6 @@ class ArbitraryWidthMemory(Elaboratable):
             m.d.comb += read_port.addr.eq(fetch_address)
             m.d.comb += self.bus.r_data.eq(read_port.data)
 
-
-
-
-            # combining shift reg
-
-            # the register itself
-
             shreg = Signal(self.fake_data_width)
             current_slice = Signal(self.backing_memory_data_width)
             lower_bits_cut = Signal(self.backing_memory_data_width)
@@ -123,15 +116,6 @@ class ArbitraryWidthMemory(Elaboratable):
 
             m.d.comb += shreg_new_bits.eq(MS_bit_index-LS_bit_index+1)
 
-#                is like a gear box but with variable upstream elnght
-
-#                thats it
-
-#                we should do this)
-
-
-
-
 
             with m.FSM() as fsm:
                 with m.State("RESET"):